Exploring the fastest production 6502 computer

[plasmo]

Inspired by renewed discussions about overclocking, I think a producible (in hobbyist quantity) very fast 6502 computer may be an interesting exercise in PC board design rules and CPU testing--and also the bragging right of having a really fast, if not the fastest, production 6502 computer.

29.5MHz 6502 is already a reality, so I want to go faster by prototyping a stacked W65C02 computer that minimizes wire length and uses faster components. I'm shooting for low 30MHz operation with the prototype. With proper PCB design, I think it can run faster than prototype so if I can achieve low-to-mid-30MHz operation with a prototype, perhaps a functional W65C02 computer can run to near 40MHz.

The design is based on CRC65 which has very few components and has demonstrated to run to 29,.5MHz reliably. To make it run even faster:
* minimize wire length and circuit loading, thus
- 3D stacking
- no parallel expansion bus
* fast 10nS RAM
* fast DOM drive
* Buffer clock through CPLD
* larger CPLD, not necessarily for speed consideration but to simplify interconnect.

Picture show the components I plan to use, and how they'll be put together. The CPLD board is the base, W65C02 in PLCC44 package is in the middle of stack and 10nS RAM is on top. 6502 has fixed pin assignments, but RAM and CPLD's signal assignments are flexible which is important to achieve short point-to-point interconnects. This should be a functioning computer with mass storage and capable of running DOS/65

Even with short point-to-point interconnect, I expect this to be a messy ball of wires!
Bill

PS, I'll publish a schematic next post, but for the assembler, namely yours truly, it is the construction guide that need particular careful consideration.

[Dr Jefyll]

Go, Bill, go!

-- Jeff

[GARTHWILSON]

Note that many of the 5V 74LVC1G__ gates have max prop. delays of about 3.4ns, and typ of 2.5ns, min of 1ns.  If your logic is simple, they might give you more speed than the CPLD will.

[Proxy]

the CPLD could also allow for hardware SPI if it has enough free logic and pins, which would be a very good way of adding expansion to the system without dragging the entire system's max clock speed down by having the CPU's bus go to a parallel expansion slot or similar.
examples for SPI based expansions: SD Cards, RTC Modules, Ethernet Controllers, Color Displays (most commonly 320x240 @ 16/24-bit), USB Controllers (like the CH367), IO extensions, Microcontrollers for other various tasks. and probably more i'm missing right now.
then again SPI can also be done in software through a VIA, which should still be pretty fast if the CPLD has not enough space on it

[AndrewP]

I'm looking forward to this!

And I'm gonna second Garth in saying that the 74LVC1Gxx ICs are stupid fast, and if they're driving low currents then they can come in under their typical propagation times.

[plasmo]

Attached are schematic, assembly guides, and a picture of W65C02 & RAM partially wired up. I built up most prototype boards using the assembly guides only, schematic is for big picture and seldom referenced during construction. In this case the schematic is even less useful because the assignment of CPLD's test points to various signals of 6502 and RAM are based on proximity to the pins, so the schematic is back-annotation of the actual construction.

Some design considerations:
* RAM chip selects are always enabled, its output enable and write enable are controlled by CPLD based on RAM memory map and clock high.
* Clock is buffered with CPLD so the oscillator does not drive 6502 directly but through CPLD.

To maximize the usable memory for DOS/65, I want to change CRC65's memory map such that:
ROM, $FF80-$FFFF
Internal I/O, $FF40-$FF7F
serial port, $FF40-$FF41
I2C, $FF50-$FF5F
SPI, $FF60-$FF6F
bank register, $FF7F
External I/O, $FF00-$FF3F
CF interface $FF00-$FF07

RAM, $0-$FEFF
Interrupt points to $200
NMI points to $300
DOS/65 TPA starts from $400

--------------------------------------------
Thanks for the comments!
To reduce loadings, I do plan to use SPI and I2C to interface to the outside world. If 6502 can really operate 35MHz or faster, it can pretty much bit-bang SPI and I2C in software so CPLD utilization is minimal.

Reasons for using CPLD are because I have it on hand and because its pins can be re-assigned to facilitate direct pin-to-pin wiring. Most important of all is CPLD's programmability which allows design changes without wiring changes AND allows the design to evolve from simplest NOP test to full-feature final design.
Bill

[kernelthread]

What's happened to that 6502? It looks like there's loads of cracks on the bottom of it.

[Proxy]

I'm pretty sure that's just flux residue.

[plasmo]

Yes, that's just solder flux residue. It is not necessary but I like to wash off the flux with IPA to get better picture of the connections.

In this picture the W65C02 is glued to CPLD "dead bug" fashion. Most of the connections to W65C02 are wired in, enough to install the RAM on top of W65C02. RAM won't be glued in, it will float above W65C02--not ideal but that's what I have to work with given the geometry of the parts.
Bill

[Proxy]

fancy!
i'm very interested in how much more speed you could get out of the system by doing this compared to a regular PCB using tightly packed SMT parts (on both sides of the PCB).
also, how fragile is that whole setup? especially when the ICs aren't glued or otherwise held together, i'd be pretty scared to touch it at all after assembly.
Maybe once you have a functional one you can put it into transparent resin to have a solid block of computing!

[BigDumbDinosaur]

plasmo wrote:

* Buffer clock through CPLD

That I wouldn’t do. CPLDs produce TTL-level outputs, but WDC processors require a clock with CMOS levels. In the case of the 65C02, the minimum high level for Ø2 is VCC × 0.7 volts, which on five volts is 0.1 volts higher than the theoretical no-load maximum of the CPLD.

If all you are looking to do is strengthen the clock signal, running it through a single gate will do the trick. If you are trying to get Ø2 as symmetric as possible, you’ll need to run it through a flop.

[barrym95838]

Is it possible (or worth the effort) to squeeze a bit more fmax out of any given design by experimenting with an asymmetric clock?

[plasmo]

This is the completed prototype with RAM installed on top of W65C02. Not a pretty sight, in fact, if ever there were an "ugly computer competition", this surely will take a blue ribbon, possibly "best of the class"! In the picture it is shown with USB-to-serial adapter and DOM disk connected.

I did applied the power and no smoke came out and there were signs of life. I'll start testing it with simplest NOP test and see what it can do.

Quote:

i'm very interested in how much more speed you could get out of the system by doing this compared to a regular PCB using tightly packed SMT parts (on both sides of the PCB).
also, how fragile is that whole setup? especially when the ICs aren't glued or otherwise held together, i'd be pretty scared to touch it at all after assembly.
Maybe once you have a functional one you can put it into transparent resin to have a solid block of computing!

This prototype is definitely delicate, not likely to survive US postal handling even with "FRAGILE" labels all over. Glue them down with clear acrylic is probably a good idea, but then I have half dozen similarly fragile prototypes just collecting dusts without additional protection. If it works well, I will likely design a pc board version of it. My feeling is properly designed pc boards should be faster, but I need to explore what is "properly designed" in the 40+MHz range.

Quote:

That I wouldn’t do. CPLDs produce TTL-level outputs, but WDC processors require a clock with CMOS levels.

That's a valid concern reading just the DC parametric data, but I have worked with this CPLD family for quite a while and there is a VI output chart hidden in the 60+ page datasheet that shows output high drives to nearly 4V, and that's conservative. My experience is clock buffered by this family of CPLD improves the quality of clock.

Quote:

Is it possible (or worth the effort) to squeeze a bit more fmax out of any given design by experimenting with an asymmetric clock?

It is worth investigating whether inverting the clock or not can extend the maximum clock frequency. It is easy to do for clock buffered with CPLD.

Bill

[plasmo]

Start testing without the DOM disk.
* a simple serial transmit test that repeatedly bit-bang out a character to serial port will run to 40MHz IF the supply voltage is raised to 5.4V. The current draw is 250mA @ 5.4V. This is likely the upper frequency limit of this board. At 36MHz the circuit is very stable. I don't have oscillators between 40MHz and 36MHz so I can't tell at what frequency it started to work reliably.
* At 36MHz, nominal 5V, current of 205mA and still without DOM disk, I'm able to serial bootstrap and load a monitor program to poke around the system. I can load a memory diagnostic and run memory test successfully.

The results are similar to my overclock experiment with W65C816 which also operated at 40MHz at elevated 5.4V but ran reliably at 36MHz at normal 5V.

I'm pleased with 36MHz because it happens to be SVGA (800x600) frequency so beam racing SVGA with W65C02 is now a possibility.

Onward to more testing with DOM disk installed.
Bill

[rpiguy2]

plasmo wrote:

I'm pleased with 36MHz because it happens to be SVGA (800x600) frequency so beam racing SVGA with W65C02 is now a possibility.

Onward to more testing with DOM disk installed.
Bill

Go Speed Racer, Go!