Strange memory write problems

[floobydust]

Just to chime in... attached is a pic of an old CPU only (2-layer) PCB I did over a decade ago. The actual design dates back to the 80's... but it's quite similar to what you have. 7400, 7430, 74138, RAM, ROM, CPU. The layout is compact and there's a 30-pin dual header for attaching I/O.

I built up 3 of these with an I/O board that uses a 65C22 and 65C51... I've run them at 4MHz without issue (with a Rockwell R65C51P4). I've also used the same Alliance memory on this board along with both 74HCT and 74HC logic chips without issues. The full design is on my github.

It's still quite odd that you're having such problems. The design is almost identical and I've never had a single issue... go figure.

[adrianhudson]

floobydust wrote:

Just to chime in... attached is a pic of an old CPU only (2-layer) PCB I did over a decade ago.

They used to say about Star Trek repeats "Stories about the future dragged up from the past". My project is the mirror image of that "Stories from the past, dragged into the future"

floobydust wrote:

It's still quite odd that you're having such problems. The design is almost identical and I've never had a single issue... go figure.

Well, since the old board no longer exists (I scavanged (most) of the parts from it for the new one), technically I'm not having any problems at the moment. But we shall see...

[adrianhudson]

Quick question.

I'm just finishing the glue logic wiring. On my schematic I have drawn the CS1 pins of my VIAs (and CS0 of my ACIAs) as pulled high to 5V - no resistor. Is this okay or should I really connect ALL pulled high signals via resistors? Do they have their own current limiting resistors internally?

Thanks!

[GARTHWILSON]

adrianhudson wrote:

I'm just finishing the glue logic wiring. On my schematic I have drawn the CS1 pins of my VIAs (and CS0 of my ACIAs) as pulled high to 5V - no resistor. Is this okay or should I really connect ALL pulled high signals via resistors? Do they have their own current limiting resistors internally?

The reason to use a resistor in the pull-up of an unused input is so if you change your mind later and want to connect it to a signal, you don't have to cut the connection to Vcc, something which can be difficult on PCBs, especially if it's on an internal layer. Otherwise there is no harm in connecting it directly to Vcc.

[adrianhudson]

Thanks Garth. Did you mean "unused" I was talking about CS0 on the 65C51 or CS1 on the 65C22. Not so much unused as pulled to logic 1. I am selecting thise devices with just CS1B and CS2B respectively.

[GARTHWILSON]

I meant unused in the sense that you're not connecting it to an output from something else. The ACIA or VIA definitely takes the logic state into account to determine when it's being selected and de-selected though. The fact that these have more than one select input allows you to simplify your address-decode logic.

[adrianhudson]

Thank you Garth

[adrianhudson]

I have completed my rebuild.

It works.

I don't (yet) have theory why it works - or rather, why the old one didn't.

The old one worked with a Rockwell 65C02 so its wiring was correct as per the schematic. It did'nt work with the WDC 65C02.

This one works and is steady as a rock. It has run a memory test program for 48 hours now.

I will think about it some more and post my thoughts soon.
EDIT: I may have found the issue. I made one change in the new build. I replaced the Alliance AS 6C62256 RAM chip with a Samsung KM62256CLP-7L which as far as I can see is pretty much identical in spec. This is the one that has just undergone 48 hrs testing.If I replace it with the Alliance chip, I get errors. I have two other Alliance chips, all the same - 6C62256 - various levels of crash.

I can't determine if it is timing problems or all three Alliance chips are damaged. I will make a ram tester with some breadboard and an Arduino when I get a moment.

Thank you once again for all the help and thoughts from everyone.

[okwatts]

Glad to hear that you are successful. Also interested that you have had the same experience with the Alliance chips that I did in my reply on Nov7. It would be interesting to understand exactly why this is the case as you have 3 and I have 2 that would make us very skeptical of where and how to use them in future designs. It is also interesting that floobydust and plasmo have not noted these issues in their experience. My hardware skills are limited so I don't expect to solve this on my own but will follow any future discussion with interest.

[Paganini]

Hi Adrian,

I'd love to see the wire wrap side of your completed working board!

[Dr Jefyll]

adrianhudson wrote:

I can't determine if it is timing problems or all three Alliance chips are damaged.

It's perhaps neither a timing problem nor damaged chips. Instead, we might be circling back to the question of whether or not the RAM's output levels sufficiently exceed their spec (which promises only TTL levels). If not, then the non-TTL-compatible WDC CPU can't be expected to operate reliably.

You didn't mention whether the Alliance chips work properly when the TTL-compatible Rockwell CPU is in use... Might be interesting to try that if you haven't already. Just a suggestion...

-- Jeff

[Dr Jefyll]

adrianhudson wrote:

I will make a ram tester with some breadboard and an Arduino when I get a moment.

Hmmm... So, will the tester be satisfied with mere TTL logic levels from the RAM? Or will it, like a WDC CPU, require something beyond TTL spec? Seems like a pertinent question, I'd say.

It would be interesting if the tester included a socket for a '245 transceiver on the RAM's data bus. Then you'd have the option to put either an 'HC245 or an 'HCT245 in there, and compare results. (You might find this idea preferable to swapping WDC vs Rockwell CPU's in your SBC... a process with which you understandably may've grown frustrated!)

Alternatively, you could 'scope the RAM's output levels while the test runs (presumably at fairly low frequency). I expect you'd get much cleaner traces than those taken from the SBC.

-- Jeff

[GARTHWILSON]

Adding to Jeff's post: See his post at viewtopic.php?f=4&t=6594 which graphically shows the differences in signal voltage thresholds, and his subsequent posts at viewtopic.php?p=83609#p83609 and viewtopic.php?p=83654#p83654 .

[adrianhudson]

Dr Jefyll wrote:

adrianhudson wrote:

I can't determine if it is timing problems or all three Alliance chips are damaged.

It's perhaps neither a timing problem nor damaged chips. Instead, we might be circling back to the question of whether or not the RAM's output levels sufficiently exceed their spec (which promises only TTL levels). If not, then the non-TTL-compatible WDC CPU can't be expected to operate reliably.

You didn't mention whether the Alliance chips work properly when the TTL-compatible Rockwell CPU is in use... Might be interesting to try that if you haven't already. Just a suggestion...

-- Jeff

Sorry Jeff, my barin [edit: whats's a barin?? ] brain wasn't working. I was thinking about "signal levels" and all your help when I posted that above and "typed timing problems"! Unlikely to be timing problems at 1mHz.

[adrianhudson]

Paganini wrote:

Hi Adrian,

I'd love to see the wire wrap side of your completed working board!

Your wish is my command:

Still have a few wires on the output of VIA2 to do but pretty well complete