CS/A65 website overhauled....

[fachat]

Hi there,

in case you haven't noticed I have overhauled my 6502 website and in this process have added a number of board schematics and even layouts in Eagle format, so you can reuse them and build your own boards.

This includes a "self-built PET 4032" with IEEE488 interface, and new CPU, BIOS and VDC boards for the CS/A65. In the pipeline (i.e. not yet published) are a SCSI board, as well as "self-built-VC1581" (i.e. a PC-style floppy interface) and more.

You can find it at
http://www.6502.org/users/andre

Andre

[blackadder]

The menu on the left isn't scrolling with the rest of the page, so part of it at the bottom isn't always visible.

Looks good otherwise from what I looked at.

[fachat]

Yes I know about the menu and it will be fixed soon.

Thanks for the comment!

Andre

[HansO]

My compliments for an impressive production and description of designs and software around the 6502!

[fachat]

Hi there,

I have updated the page again. It now contains an "auxiliary CPU" - a CPU that detects bus errors on a 6502, halts the main CPU, takes over control and "fixes" the bus error.
The system can currently detect write protect faults, segmentation faults (no memory available at used address), or even "No execute" protection fault.

Have a look at http://www.6502.org/users/andre
or http://www.6502.org/users/andre/csa/auxcpu
for the auxiliary CPU.

André

[kc5tja]

fachat wrote:

Hi there,

I have updated the page again. It now contains an "auxiliary CPU" - a CPU that detects bus errors on a 6502, halts the main CPU, takes over control and "fixes" the bus error.
The system can currently detect write protect faults, segmentation faults (no memory available at used address), or even "No execute" protection fault.

Have a look at http://www.6502.org/users/andre
or http://www.6502.org/users/andre/csa/auxcpu
for the auxiliary CPU.

André

Man, what started as a small project has now turned essentially into an open-source PET implementation with all sorts of bells and whistles.

I'm hoping my Kestrel can achieve similar stature. Although, I'm hoping to place an MMU inside the FPGA, such that it takes full advantage of the 65816's ABORT exception pin.

Alas, I need to write its BIOS first though, even before I design the hardware for it. (Thankfully, I wrote a convenient emulator for how I'd *like* to see it running to start with.)

[fachat]

Quote:

I'm hoping my Kestrel can achieve similar stature. Although, I'm hoping to place an MMU inside the FPGA, such that it takes full advantage of the 65816's ABORT exception pin.

I have a 65816 board in the works, but without an MMU. But it uses my standard bus. I still have to check that the schematics to slow down the 65816 from 8MHz to 1MHz using RDY really works...

The article on http://www.6502.org/users/andre/icap/mp.html (I forgot to post this link before) goes into more detail how this stuff works.

Quote:

Alas, I need to write its BIOS first though, even before I design the hardware for it. (Thankfully, I wrote a convenient emulator for how I'd *like* to see it running to start with.)

I need to overhaul my GeckOS operating system to improve its performance with file transfers (load/save), and define networking support (e.g. using a specific serial interface...... :-)

André

[fachat]

Here I go again.

I have finally managed to put up a power supply board (using a PC power supply as base, though), and a VIA prototyping board. And a logic probe.

Have
André

http://www.6502.org/users/andre

[fachat]

Hi all,

I have added to my site a new version of the single-board "Gecko" Computer. Now a board layout is available. It features infrared signal output to control the stereo, a Commodore serial IEC bus interface, an RS232 interface, and a small 4bit in/4bit out port (e.g. for a keyboard)

It can be used as single-board computer, or can use other CS/A boards like SCSI, or PETIO. Using jumpers and removing some ICs, it can even be used as a simple I/O board for another CS/A system.

http://www.6502.org/users/andre/csa/gecko/index.html

Additionally I have added my new MMC- and SD-Card interface to the page.

http://www.6502.org/users/andre/csa/spi/index.html

Have fun
André

[fachat]

Again an update of my CS/A website. The main update:

A hardware design lesson I got from Bil Herd, the principal designer of the Commodore 128.
http://www.6502.org/users/andre/icaphw/design.html

André

[kc5tja]

If Bil was "principle," where does that leave Dave Haynie?

Funny the associations folks have: you with Bil, and I with Dave. Hahah

[BigEd]

fachat wrote:

A hardware design lesson

Fascinating! I may have to avoid DRAMs for ever.

[BigDumbDinosaur]

BigEd wrote:

fachat wrote:

A hardware design lesson

Fascinating! I may have to avoid DRAMs for ever.

I have no plan to use DRAM in the stuff I'm concocting. Refresh is a royal pain in the...er...backside. I won't even go into the timing issues as the clock rate goes up.

[kc5tja]

C'mon -- admit it -- you wanted to say that it was a royal pain in the CAS...

[BigDumbDinosaur]

kc5tja wrote:

C'mon -- admit it -- you wanted to say that it was a royal pain in the CAS...

There's a good idiomatic expression in Spanish that conveys the same message, but without using any references to anatomy: Un dolor de huevos. But, you're right. It would be a pain in the CAS...and elsewhere. DRAM is like the IDE interface: both are used because they are cheap.