I know the max frequency is voltage dependant, but are the timings given in nanoseconds dependant on the voltage or frequency? Or is it more complex and depends on which specific timing I'm referring to?

The chart on page 25 of WDC's 6502 datasheet only gives timings between 5V (14 MHz max) to 1.8V (2 MHz max). I intend to use 5V at 1 MHz.

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I think most of the times are absolute, varying with voltage. The only exceptions I'd expect would be minimum cycle times, which of course define the frequency. But I haven't looked carefully at the table.

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Thanks again BDDinosaur! Based on both responses, I believe I should refer to the 5V (14MHz max) column since that is the voltage I intend to use. This goes a long way towards furthering my understanding of the timing diagram and the animated timing diagram that was linked in Garth's primer.

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This question arose mostly due to me second guessing what I thought I already knew. Its good to have confirmation that I was on the right track. Thanks to BDDinosaur and Garth Wilson, I have a much better understanding of what I'm looking at in the datasheets.

Now, I'm confident that I can crunch numbers this weekend and make sure the timings on everything I plan to use is going to work. I'm not blindly copying anyone else's working design because I want to actually understand how and why it does what it does.

The idea I have at the moment is to "borrow" a memory map from elsewhere on this forum (I forget who posted it):

0000-7FFF 32K RAM (eventually, I want to load programs from an SD card)
8000-83FF 1K I/O (far more than I think I will need, famous last words...)
8400-FFFF 31K ROM (would basically function like a BIOS in a modern PC, handles keyboard, 128x64 LCD, SD card)

I think I figured out how to achieve this:
74HC00 Quad NAND gate
( NOT(A15) NAND CLK ) = RAM_CS\

74HC682 { Inputs 2 bytes, outputs P=Q or P>Q }
A15-A10 connected to P, lowest 2 bits of P tied to ground
10000000 hard wired to Q
P=Q = I/O_CS\
P>Q = ROM_CS\

Primary goal: Get it working and understand it well enough to successfully explain it to someone else.
Secondary goal: Have the ability to write and compile programs on my PC, transfer them to an SDcard (just copy it in Windows explorer, not make a disk image), then load and run them on my 6502 computer - this will most likely involve using an Arduino to handle the FAT32 file system.
Long term goal: Port BASIC to my 6502 computer.

Ambitious, I know, but I think I'm up to the task.

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Nice goals, good luck with them! Reading FAT32 from SD cards is not out of the question even without an Arduino in between - if you're happy to borrow code, I shared a fairly compact implementation on github a few years ago, and have been using it pretty much unchanged since then, especially for large data files.
You can see it here if you like: https://github.com/gfoot/sdcard6502/blo ... Library.md

Gfoot, your writeup on the SD card, which I found through HackaDay, is what gave me the idea to use one in my project!

I'd be happy to borrow your code, and of course give you credit, but I gotta understand it first. One thing at a time. The main reason it's taken nearly a year from buying the kit to put anything on a breadboard is all the research I've been doing. In order to understand this, I need to understand that, but before I can, I need to know how this other thing works... six rabbit holes later, it's 3am and my brain is fried. LOL! I'm sure everyone in this forum has been there, done that at some point. Thanks for the good luck wish, I'm going to need it!

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[s]Will do, once I get it drawn up.[/s]

BTW: if a picture is worth 1,000 words, is a video worth 60,000 words per second?

Here is my proposed address decoder:


Also, the datasheet for my RAM has this note about the write operation:


I initially thought this means that if R/W somehow wins the race and goes low before or at the same time as CE, that the write operation won't work, but Ben Eater built his computer with R/W going straight to WE seemingly without any issues. So, what does this actually mean?

Timing diagram it refers to:

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Indeed, as the target speed is 1MHz, it's not fair to criticise that the design won't go at great speeds. It's not meant to, and the comment is just a temptation to scope creep.

Keep it simple, stick to your goals, and get it working. Plenty of possibilities for going further, after you have something working.

Exactly! I want to build a computer that I can understand, not brag about how fast it goes, although I may brag that I understand every last bit of how it works (once I do)...

When I got my first PC, I wondered how it "knew" where to look for DOS. Just a couple years ago, I installed Arch Linux on a computer - by hand "the Arch way", no fancy automated installers. I learned the BIOS is hard coded to look in the first 512 bytes of whatever storage is available. Now, after researching the 6502, I'm assuming modern CPUs also have reset vectors or equivalent that are hard wired and tell them where to look for the BIOS startup routine.

As I stated before, one of my goals is to mimic an old pre-Pentium era PC design (386, 486), using the ROM as a sort of BIOS, which loads programs from some sort of mass storage, most likely an SD card.

I rewatched Ben Eater's bus timing video https://www.youtube.com/watch?v=i_wrxBdXTgM&ab_channel=BenEater again and this time I stopped it multiple times to make notes on my own timing diagram, similar to how he did it. Even he admits that the 6502's timing diagram is a bit convoluted. I grabbed a screenshot of the PDF, threw it into Paint.Net (Photoshop for poor people), added the nanosecond timings directly to the diagram, and added the definitions of the abbreviations along the side and footnotes on the bottom. Everything is on one page and I don't have to flip back and forth between two or three pages any more.



This went a long way towards fully understanding what I was looking at! It also put in plain view why chip select is tied to the high end of the clock cycle.

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One thing I quite like to try to make clear, although it verges on the pedantic, is that for almost all purposes the rising edge of the clock is not a timing reference. It's a very convenient point in the cycle and it's very often used, in effect, to qualify some control signals to arrange that the design is safe and correct. However, it is just a point in the cycle, and if a design had another timing reference which falls neither too early nor too late then it would do just as well.

In your diagram - which is a great idea - we see just two signals referred to the rising edge. One is the rarely-used input SOB. The other is the validity of the databus during a write cycle. As that's not a control signal, there's no safety aspect there for normal designs - the constraint of interest is the receiving device's need to see stable data, which will normally be measured as a setup time, in advance of the falling edge.

As I say, a slightly pedantic point. But I think it helps to have a correct view of what causes what, as well as when things happen.