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And again—if you have a slow RAM that needs more time, you can select it before Φ2 rises, as long as you don't bring its WE\ line low until Φ2 rises. That will require deriving separate RD\ and WR\ signals though, for its OE\ and WE\ pins, respectively, like BDD shows here. If your RAM is fast enough (which it probably will be, as 10ns SRAM has been common and cheap for a decade or two), the simpler one-chip glue will work fine.
- GarthWilson
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Something to consider is many non-65xx devices, primarily those with an Intel-compatible bus interface, will respond faster if /CE is gated before /OE or /WE. This behavior includes many different kinds of SRAM. For this reason, I don’t qualify chip selects with Ø2. Instead, I qualify /OE and /WE with Ø2 in a way that results in one of those signals being asserted within one gate delay after Ø2 goes high.
- BigDumbDinosaur
When I first saw R/W gated with the clock in another post (
download/file.php?id=16196&mode=view), it got me wondering why it works.
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I've been using this circuit since the 80's without issue... even with newer 32KB SRAMs.
- floobydust
These really answer my question regarding gating the clock with CE vs R/W. I was already familiar with the "how", now I am beginning to understand the "why".
Thanks for all the help, both of you!
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