GARTHWILSON wrote:
Quote:
I have the divider value connected to a 6522 port A. If the direction of the port is switched to output what value appears on the pins?
whatever is in the port's output registers. In fact, that's how you can emulate an open-drain output (although it can't handle high voltages). You put a 0 in the output register for the desired bit; and then to pull the pin down, you make it an output, and to let it up (via a pull-up resistor), or to read it, you make it an input. Changing the data direction doesn't change what's in the output register.I just realized from your response that his design is using your memory modules, and went and read your datasheet. It is much clearer now.
If I am read and understanding the diagram right, this SBC design features a 65C816 CPU and a '573 latch for capturing the bank byte. The 24 address lines from CPU and the latch are routed through three '245 bus transceivers. The upper two address lines, A22 and A23, feed into a pair of '139 2-to-4 decoders that feeds the enables (WE0/1 and OE0/1) for the three memory modules, while the next three address lines, A19-A21, are routed to a '138 3-to-8 decoder to feed the chip enables on the memory modules. The data lines also have a '245 bus transceiver between the CPU and the memory modules. I assume the '245 transceivers are present to allow tri-stating. The '244 appears to be taking the RWB signal from the CPU an sending it on to the enables for the '139 2-to-4 encoders that enable the memory modules, but one of those has an inverter on it - I think this means that one '139 sends logical true to OE0/1 on the memory modules, or the other sends signals logical true to WE0/1.
The FPGA is connected to the data lines, again with a '245 bus transceiver between the FPGA and the data bus. About half the address lines appear to be connected, too. The FGPA is connected to the VDIP2-32 via four-line serial. It also looks to generate 6-bit RGB color (2 bits per color channel) and HSYNC and VSYNC signals for VGA output, and an audio signal that goes to an LM386 op-amp.
It appears to be a mixed voltage design, with most chips being fed 5V, 3.3V for the LVC family parts, and 12V for the LM386 op-amp.