Updated the CPLD trainer to rev1 pc board to fix known pcb errors. I also added a new feature: multiple 40-pin CPU are co-located on the pc board. Because CPLD can be reprogrammed to accommodate different CPU, the same pc board design can accommodate different CPU as long as the CPU is in 40-pin 600-mil DIP package. Each CPU is located in the same board area but offset by 0.1". In theory 6 different CPU can co-located in the same area but rev1 pc board implemented 6502, Z80, and an uncommitted 40-pin DIP which can be any 40-pin CPU with connections manually wired in. This is part of my efforts to develop common platform for retro-computers.
Bill

Hi Bill Looks interesting, I have hardly any Z80 knowledge except having played with CP/M. I have slightly more 6809 knowledge but that is from the 1980's. I followed your link to the Retrobrew computers forum and can see that you have been very busy with your new project ideas. So many interesting projects and not enough time!

By reprogramming the CPLD for Z80 timing, populating the trainer with Z80, 512K RAM, 512K flash and installing ROMWBW software in flash, it booted up and able to run CP/M with 384KB of ROMdisk and 256KB of RAMdisk. This is sufficient to explore CP/M. For more disk space a compact flash board can be added to the expansion bus.



Replace Z80 with W65C02, reprogram the flash, and reprogram the CPLD, it becomes a 6502 SBC.


I have several 6809. I can wire the uncommitted socket for 6809 and see what it takes to get 6809 running on this board.
Bill

Very promising for retro investigators especially if 6809 proves out. One board for comparing the major players in the vintage age.

Generic Front Panel, Introduction

The trainer has six 7-segment display, 4 digits for addresses and 2 digits for data. It also has a PS2 keyboard mini-DIN connector to make it a standalone computer along with a VGA interface. I discovered another application for the PS2 keyboard with my recent exploration of PS2 interface; the simplicity of PS2 protocol makes me realize that the modest CPLD in the trainer has sufficient logic to build a "front panel" with 7-seg display as output and PS2 keyboard as input without the help of a microprocessor. The concept is generic so the core front panel logic can be reused for different processors.

The purpose of the front panel is to display/modify contents of the system RAM while the microprocessor is inactive. Once the processor is active, the front panel displays the processor's address/data while single step the processor or run it continuously. (an aside: while the front panel works primarily with ROM-less system, it maybe possible to work with EEPROM like AT28C256. It may be interesting to display/modify contents of AT28C256 using the front panel but I have not worked out the details, yet.)

Trainer has a modest CPLD with 128 macrocells, so the challenge is to pare down the front panel functionalities to fit this limited CPLD. The following is a description of barebone front panel functions:

The front panel has two modes of operation, data entry mode and run mode. In data entry mode the processor is inactive and relinquish its bus mastership. The keyboard takes over the address/data bus whose values are displayed on the six 7-seg display. The keyboard can display and modify the system RAM's content with few simple single-key commands. The single-key commands are:

* Space key reset address field to 0x0
* Enter key writes data on display to current memory location, then reads and displays content of next memory location
* Backspace key decreases current memory location by one, then reads and displays the memory content.

The keys 0-9, a, b, c, d, e, f are hexadecimal input for the 8-bit data field. Following an Enter keystroke, a hexadecimal key input will modify the most significant digit; next hex input will modify the least significant digit; if there are additional hex input the modified digit will alternate between the most significant and least significant digit.

The 16-bit address register is not directly modifiable. Space key reset address register to 0x0 and read/display content of RAM at 0x0; Enter key writes current data to current address, increment address register and read/display content of RAM of the updated address; Backspace key decreases the address register and read/display content of RAM of the updated address.

The decimal points of the 7-seg display are lit to show operator that it is in data entry mode

* Escape key toggles between data entry mode or run mode. Once entering the run mode, the processor becomes the bus master and actively in control of the address/data bus. The "Wait" signal (or equivalent) is asserted to keep processor from running (this assumes processor is CMOS and retain its internal states while stopped). The 6-digit display shows the address and data as driven by the processor.

The keyboard can issue two commands while in run mode:
* "S" key negates the "Wait" signal for a clock for every "S" key press, effectively single-step the processor.
* "R" key negates the "Wait" signal so processor can run continuously. Press "R" again asserts the "Wait" so processor can be single stepped with "S" key or run continuously again with "R" key.

Next session I will describe the CPLD design in details.
Bill

I am starting to assemble the PCB and have Z80, 6502 and 6809. Interested in 6809, as well. 6809E with external Q/E via a quadrature clock may be interesting with this device, though.

I have not tried 6809, yet. It needs nearly 40 manual wiring; I have a bit of time this weekend so I may give it a try.

Are you using Altera(Intel) CPLD or Atmel? If you are new to CPLD, getting CPLD tool chain to work is probably the most challenging part of the project.
Bill

I have on hand EPM7128SLC84-10N's. I found a thread with a good discussion about programming them under the "CPLD trainer on eBay" thread.

One of the CPLD hurdles is making sure EPM7128S can be programmed. Many used EPM7xxxS have their JTAG interface disabled, so a special programmer (which is no longer obtainable) is needed to re-enable the JTAG interface.

I built up another CPLD trainer and wired the uncommitted 40-pin socket for 6809. I'm surprised to see how similar the pin assignments of 6809 and 6502 are. So wiring address/data/control from 6502 to 6809 are fairly simple and neat. 6502.org is not the place to talk about 6809 so I'll continue the exploration of 6809 on retrobrewcomputers.org.
Bill

I read a recent post on retrocomputingforum.com on the topic of how far 6502 can be pushed. Drogon mentioned 2MHz 6502 Beeb can do BadApple animation at full VGA resolution. Very impressive feat at 2MHz! So it makes me wonder whether 6502 overclocked to 25.175MHz operating as a VGA controller can receive compressed serial data, decompress and drive VGA image at 640x480 at 20 frames/sec rate? I know I can do static 640x480 picture with 25MHz 6502, but displaying animated video is a more difficult project. The CPLD trainer has bigger CPLD so it may handle the challenge of animated monochrome video at full VGA resolution. I'm going to give it a try...
Bill

Greetings,

I have used this for quite a few projects, but it is mostly for 27Cxxx and like devices. But definitely like ROM emulators up to the point you can flash in circuit.


https://www.tindie.com/products/mygeekyhobby/eprom-emulator-diy-arduino/
-William

To operate the trainer as a VGA controller I must first make sure it can run 25.175MHz. So I modified the SBC design of lesson 10 as follow:
* add a wait state to flash access from $F000-$FFFF,
* modify the baud generator to divide 25.175MHz by 13.5 which resulted in serial clock of 116550 or 1.1% faster than the standard 115200,
* replace 55nS RAM with 25nS RAM, 25nS RAM is still not fast enough on paper, but it is what I have on hand.

The modified trainer appears to work at 25.175MHz. Adjusting the baud clock generator and testing with 29.5MHz clock, I see it'll boot and execute the monitor commands but memory diagnostic is failing intermittently so I believe the design is on the hairy edge at 29.5MHz. I'm a bit disappointed because CRC65 is able to run reliably at 29.5MHz using the same 25nS RAM. Perhaps the reason is because CRC65 is a spartan design with PC board half the size and minimal set of components where the trainer is twice as large pc board with RAM, ROM, Z80 socket, expansion connector and the 25nS RAM is on a SOJ-to-DIP carrier board. The added capacitance probably pushes it to the hairy edge at 29.5MHz. The good news is it should have good design margin at 25.175MHz. Design file for 25.175MHz is attached for people wanting to try it.

Next step is to prototype a VGA connector hooking up to spare CPLD I/O pins. I also need to modify the CPLD to duplicate the design of earlier VGA controller where software read graphic data located from $4000 to $DFFF in a tight loop and a 8-bit shift register loads the data and shifts out at 25.175MHz pixel clock. The RAM program area is $0-$3FFF and the ROM monitor is located at $F000-$FFFF. $E000-$EFFF is I/O area.

After that I'll figure out how to compress BadApple images offline, send it serially to this board which must decompress and updates the graphic data during the vertical retrace period at the rate of 20 images per second.

One step at a time...
Bill

The project is creeping along--way too many distractions. I added a VGA connector and wired HSync, VSync to spare pins. VGA's RGB signals are driven with repurposed I2C signals. The 31KHz HSync is generated by dividing 25MHz by 800 in CPLD hardware. HSync also drives 6502's interrupt such that 80 bytes of video data are shifted out in the interrupt service routine to form 640 pixels per HSync. Vertical Sync is generated in software. This scheme works well enough to display a static 640x480 image. The challenge is how to display 640x480 video.
Bill

Very nice, Bill!

Can you give us a little more detail, please, re the ISR for NMI? I have a feeling there's a trick involved, but I'd like to hear you explain it.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Jeff,
I used IRQ instead of NMI, but now you've mentioned it, NMI may be a better choice, assuming it is turned off initially and can be turned on by writing to a magic location.

The program always waits for IRQ while executing WAI instruction so it has a consistent interrupt response time. The IRQ service starts off with some NOP as front porch followed by 80 set of the following instructions:
.byte 3 ;single cycle NOP
LDA ($b0),y
INY

Each set of instructions take 8 clocks to execute; ZP $b0,$b1 points to graphic data in RAM region $4000-$DFFF; hardware in CPLD snoops memory access between $4000-$DFFF and load the data into a 8-bit shift register that shifts data out at 25.175MHz. Oh, maybe this is the trick you are thinking of: the original graphic data needs to be reformatted to fit 3 lines per page so LDA ($b0),y does not cross page boundary. The reformatting is done to the original graphic data during the vertical retrace period.

While 6502 has some spare capacity to receive/store serial input during each horizontal retrace, processing of the serial data needs to be done during the vertical retrace period.

Attached are the VGA test program and schematic of CPLD (the VGA-related logic is in the bottom 1/4 of the CPLD schematic).
Bill