Turing 6502 youtube channel.

[Turing6502]

Hello all. I'm Matt Regan. I've made a bunch of youtube videos on the 6502, from a Turing Machine perspective.
The different playlists are at varying levels of completion, but here is a basic breakdown of what is where and the logic behind the progression

1) Apple 2 wire-by-wire build.
https://www.youtube.com/playlist?list=P ... Z-hC8qJsqO
The idea with this playlist is to build an Apple 2+ using a 65C02, the focus is on the environment outside the microprocessor. About half the videos so far are on the 65C02 memory interface and the other half are on video signal generation. Still have the floppy and keyboard interface to go.

2) Pure Turing.
https://www.youtube.com/playlist?list=P ... 12HLar0iF8
This build is a very simple Turing machine with a finite state automaton and bidirectional sequential access memory. It's a breadboard build and it is very slow because of the sequential access, but it does emulate the 6502 with minimal hardware (essentially 1-bit operations). I plan to add a simple Memory Address Register, which is essentially a shift register with its outputs connected to the address lines of the memory. The idea is to show just how much a MAR with random access memory speeds up the machine.

3) Turing 6502
https://www.youtube.com/playlist?list=P ... Gl0QrhX9p7
This is a Turing Machine, but it uses 256 symbols (8-bit) and three Memory Address Registers, one for local variables within the emulation and one pair for the main Apple 2 memory (64K). This series shows that we can reach real-time with this design. I go over the state machine diagrams for most of the 6502 instructions here. These are a little easier to follow than the diagrams for the 1-bit machine.

4) Turing To Von Neumann
https://www.youtube.com/playlist?list=P ... fP22XoZujC
In this playlist, I slowly transform the build from being a Turing machine into a more conventional Von Neumann architecture by adding features such as an accumulator, an ALU, a Program Counter, an Instruction register and a status register one at a time. Does anyone want to guess what the FSA in the original Turing machine becomes?

Looking forward to some feedback and suggestions.

[BigEd]

Ooh, a rich seam - thanks!

[tmr4]

Very interesting. Thanks. In the learned something new everyday category:

I never thought of placing a wide IC over the breadboard power rail. This frees up the tie points that would have been covered by the chip, though perhaps it results in a slightly less compact layout. Unfortunately, it doesn't work with a machined socket.

[Turing6502]

tmr4 wrote:

I never thought of placing a wide IC over the breadboard power rail. This frees up the tie points that would have been covered by the chip, though perhaps it results in a slightly less compact layout. Unfortunately, it doesn't work with a machined socket.

It actually works surprisingly well. The distance is such that you don't need to bend the pins (much) before inserting them. I've never had one spontaneously pop out. It does cost density, but I use it for buses mostly. Yep, it's too wide for machined sockets.

[Turing6502]

The next part is up
https://youtu.be/4n8b_43MleA

This is the second part of the Pure Turing build.

[Paganini]

I watched the first couple of Apple ][ videos. I really like the split-screen view where you show the schematic along-side footage of your actual working practice. I'm going to try that insulation sliding trick on my next project!

[Turing6502]

Paganini wrote:

I watched the first couple of Apple ][ videos. I really like the split-screen view where you show the schematic along-side footage of your actual working practice. I'm going to try that insulation sliding trick on my next project!

Great thanks. The trick is to pre-stretch the wire relative to the shielding. Stip one end, hold the bare wire in one hand and the shielded wire in the other with about 50cm (20 in) wire in-between. Stretch the wire by about 0.5 cm (1/5 in). It makes the shielding much easier to slide.

[Martin_H]

I'm going to reply and say that the content in his videos is top notch. It's definitely worth the time to watch it.

Given that you showed 6502 assembly for a Turing machine, I imagine it would be possible to have a 6502 emulate a 6502. Not a good idea, but certainly possible.

[Turing6502]

Martin_H wrote:

Given that you showed 6502 assembly for a Turing machine, I imagine it would be possible to have a 6502 emulate a 6502. Not a good idea, but certainly possible.

Yes indeed, i'm planning to do that in an upcoming video. Not practical, but it shows the idea of one machine emulating another including itself. It was part of Turing's proof for the entsheidungsproblem.

[BigEd]

(A schoolfriend of mine borrowed my Compukit while I was away, and wrote a monitor with a single-stepping capability which was in effect an emulation of 6502 on 6502. It was possible, he said, but terribly slow, to run the monitor within itself.)

[Turing6502]

The next video is up. It is the bring-up for the 4 symbol Turing machine emulating a 6502 (rather slowly)

https://youtu.be/aPCyUSnOuO4

[Turing6502]

Next one is up, https://youtu.be/vkU06umK2xs
This covers the logical instructions ASL, LSR ROL and ROR

[Sheep64]

I wonder if 6522 is Turing complete? I suspect yes because the interaction between I/O and counters allows a deterministic sequence of bus cycles to perform computation.

BigEd on Mon 13 Jun 2022 wrote:

(A schoolfriend of mine borrowed my Compukit while I was away, and wrote a monitor with a single-stepping capability which was in effect an emulation of 6502 on 6502. It was possible, he said, but terribly slow, to run the monitor within itself.)

I'll be very impressed if 6502 on 6502 simulation either requires less than 2KB of program or runs no worse than 30 times slower. Assuming that the smallest implementation was desirable, I assume that it was possibly 50 times slower.

I've dabbled with 6502 on 6502 simulation. It started as 65C02 on 65C02. After establishing that the native call stack can be used by the simulator and that RegP is best hidden on top of stack, simulation is focused on RegA, RegX and zero page. While RegY can be held in its native register, I chose otherwise because this eases extended uses, such as additional index registers or vector operations. When not held in native registers, RegA, RegX and RegY may be held in memory locations which are compatible with KIM-1 monitor firmware.

If RegX is set to zero in a few places, 65C02 simulation can be written in NMOS 6502. To be pedantic, it is possible to implement the ROR bug workaround. This allows 65C02 on 6501 - with a mere factor of 30 performance penalty. It that isn't slow enough, is possible to include decimal mode workarounds. In particular, this allows decimal operation on systems without decimal support. Going the other way and expanding outwards, I found that it is possible to implement a fictional aggregate of RegB from the draft 6501, RegQ from the failed 6516 and RegZ from 65CE02 while reserving 11x1x100 as prefixes for 16/32/64 bit extensions. With minor speed penalty in the simulation, it is possible to substitute absolute address mode with abs,Z. However, good luck implementing all of this in less than 6KB. Ordinarily, it not possible to nest simulations due to conflicting use of zero page. However, with further performance penalty, for each nested simulation, it is possible rotate memory around by one page or more.

One of the many advantages of writing a ridiculous extension of 6502 (with two accumulators, two flag registers, three or more index registers, additional addressing modes and vector extensions) is that it can be programmed using your favorite assembler, as part of your preferred workflow.

[Turing6502]

Sheep64 wrote:

I wonder if 6522 is Turing complete? I suspect yes because the interaction between I/O and counters allows a deterministic sequence of bus cycles to perform computation.

BigEd on Mon 13 Jun 2022 wrote:

(A schoolfriend of mine borrowed my Compukit while I was away, and wrote a monitor with a single-stepping capability which was in effect an emulation of 6502 on 6502. It was possible, he said, but terribly slow, to run the monitor within itself.)

I'll be very impressed if 6502 on 6502 simulation either requires less than 2KB of program or runs no worse than 30 times slower. Assuming that the smallest implementation was desirable, I assume that it was possibly 50 times slower.

I've dabbled with 6502 on 6502 simulation. It started as 65C02 on 65C02. After establishing that the native call stack can be used by the simulator and that RegP is best hidden on top of stack, simulation is focused on RegA, RegX and zero page. While RegY can be held in its native register, I chose otherwise because this eases extended uses, such as additional index registers or vector operations. When not held in native registers, RegA, RegX and RegY may be held in memory locations which are compatible with KIM-1 monitor firmware.

If RegX is set to zero in a few places, 65C02 simulation can be written in NMOS 6502. To be pedantic, it is possible to implement the ROR bug workaround. This allows 65C02 on 6501 - with a mere factor of 30 performance penalty. It that isn't slow enough, is possible to include decimal mode workarounds. In particular, this allows decimal operation on systems without decimal support. Going the other way and expanding outwards, I found that it is possible to implement a fictional aggregate of RegB from the draft 6501, RegQ from the failed 6516 and RegZ from 65CE02 while reserving 11x1x100 as prefixes for 16/32/64 bit extensions. With minor speed penalty in the simulation, it is possible to substitute absolute address mode with abs,Z. However, good luck implementing all of this in less than 6KB. Ordinarily, it not possible to nest simulations due to conflicting use of zero page. However, with further performance penalty, for each nested simulation, it is possible rotate memory around by one page or more.

One of the many advantages of writing a ridiculous extension of 6502 (with two accumulators, two flag registers, three or more index registers, additional addressing modes and vector extensions) is that it can be programmed using your favorite assembler, as part of your preferred workflow.

I'm just planning to write a simple turning machine emulator and then running the 6502 code 1-bit emulation. It will be excruciatingly slow (probably x1000 slower) but it will prove the point that 6502 <- simple turning machine <- 6502 can be done. It shows that the 6502 is in fact a turning machine (which we already know). I'm keen see how you go with a much more performance oriented model.

[Turing6502]

Next part of Pure Turing is up, this goes over the memory system is formed.

https://youtu.be/wVMkDU9PRZQ