Does anyone have any idea how to put a 65C816 on a 16-bit external bus?

I realize that it would still take two 8-bit writes, internally, to write-out 16 bits, so you're still at 1/2 the full clock speed (externally). But, does anyone know of a way to basically latch two 8-bit writes onto a 16-bit bus, and then "send" them, so that you would have, effectively, a 16-bit external bus at 1/2 the speed the '816 is running at internally?

Jonathan

Hi, I'm on mobile so I can't draw a schematic of this, but thinking out loud:
- what would be the expected behavior if the CPU is in 8 bit mode (M=1)? I don't think it is realistic to have it always be 16 bits, things like hardware peripherals usually work best in 8 bits. Might need to split your memory map in a 16bit section and a 8bit section. You can then integrate this decoded address to the mechanism that triggers the cycle counter. You could potentially also integrate M for additional safety.
- the second byte can come straight from the data bus, but you'll need an 8bit register to memorize the n-1 byte - just wire the cpu clock to the register to always have the n-1 bit memorized
- you can use a single flip flop to detect even/odd cycles, it needs to be reset after each read
- then, when you're writing, M=0, the right address is presented and the cycle is odd, you can pass through the write pulse that you use for the rest of the circuit.
- of course checking M means that it won't work with M inverted. You're probably not interested to write there in 8 bit mode but if you wanted both another type of triggering would need to be implemented in that case

Not a circuit I've built, but I'm curious how you end up implementing it.

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I had thought about this too.

You'd need to map this area twice, one address range for 8bit access and the second range for 16bit.

In the 16bit area a write to the even addresses would latch into a holding register. That would then be sent onto the 16bit bus along with the value written to the odd address afterwards.

Reads would work the same way. Read the even address latches the upper byte that can then be read on the odd address (even+1)

The reason for this order is thst the 65816 writes low byte first on 16 byte accesses that are of course split due to the 8bit data bus (at least I think I remember it in this order, pls verify).

This should even be relatively simple to implement.

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

So, in theory, you could do the same for every n 8-bit words. I wish I could write more, more easily, but I’m on my phone, too.

So, in your model, what sort of latch would be required to do it?

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What's an additional VIA among friends, anyhow?

i'm currently using a 65816 with 16-bit wide SRAM.

reading from a 16-bit bus is easy:

you do the bank address/data bus seperation like normal
but you reserve one of the address lines (A0) to select either the upper or lower 8 bits of the bus to be read. A0=0 -> Select lower 8 bits, A0=1, select upper 8-bits. (or the other way around, doesn't matter)
for the actual selection you just use an 8-bit Multiplexer or 2x 8-bit Tristate buffers with the outputs connected together to the CPU, and with A0 connected directly to the Enable line of one of them, and inverted A0 going to the other.

writing is more complex though, if you just want to hook up to some SRAM then it's also very easy as 16-bit wide SRAM chips almost always have Byte select lines so you can tell them to ignore either half of the data bus. allowing you to just put your 8-bit value onto both halfs of the bus and only allow the SRAM to take one of them depending on A0's current state.

but if you got some actual 16-bit devices, honestly just use a 65c22 and use both ports togther as a 16-bit wide buffered bus.

also, damn you people, stop giving me ideas for FPGA softcores!
just imagine it, a true 16-bit 65816 with a full 24-bit Address bus and 16-bit Data bus... what a project that would be!

My approach I described would basically only work for 16bit IO. But for that it would allow writing 16bit values either with two 8bit opcodes or with a single 16bit opcode. MX would not be needed just proper programming.

Random access would be way more complicated if at all possible. As the device or memory does not know about 8bit accesses accessing 16bit values on odd addresses probably wouldn't make any sense. How would you write an 8bit value? You'd need to fetch the 16bit word, replace half of it, and store the word again. Way too complicated.

Opcode fetches could probably fetch a 16bit word and pick the one that is needed. Not sure if a buffer makes sense here as speed cannot be improved on CPU side anyway. And you would need branch/jump detection to invalidate the buffer. VDA/VPA could select the type of access.

(Sorry on the mobile but hope that clarifies it a bit)

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

In another post I made suggestions for interfacing to a bus that hosts 16-bit devices only. And perhaps that's all you need, Jonathan. (If you also have 8-bit devices then they can "live" on the 8-bit side, upstream of the circuitry I've shown.)

I'm not convinced there's any need to monitor the MX output. I assume (but this might be wrong) that the 16-bit device(s) won't ever be required to perform an 8-bit access. So, simply placing a 16-bit device's address on the address bus is sufficient to say the access will be 16 bit.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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Proxy was writing in parallel ... nice info on the SRAM!

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Jeff, I'd put the buffers all on the low byte, because as far as I know 16bit access on the 65816 is low/hi, isn't it?
This way you could simply write a 16bit value from a register with a single opcode

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Yes, but remember the goal is to accommodate the device's need to read or write 16 bits all at once.

For a read, the 16-bit transfer from the device happens on the first of the two '816 cycles. And for a write, the 16-bit transfer to the device happens on the second cycle. The details are in the post I linked.



-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Thanks Andre, Jeff, Garth, and everyone else! I'm glad I was able to raise an interesting topic/issue. Anyway, yeah - any 16-bit devices on the 16 bit side would only be making 16 bit reads and writes on the data lines.

I actually though about trying with a fast-clocked shift register, but it really made no sense.

Meh stupid me. Quite obvious. Thanks for pointing out. That happens when you post on the mobile in between doing other stuff ...

André

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Lol, I hear that! And, yet, you still make plenty of sense!

Jon

This process scales to 32 bit using one 74x138 or 64 bit with two 74x138. The catch is that read-modify-write doesn't work as expected. 16 bit reads would be from addresses where A1=0 but writes would be to addresses where A1=1. Also, depending upon choice of peripheral, it may be necessary to AND (active low OR) /3 and /4 to obtain a general wide peripheral bus strobe.



If you make the data bus 16 bit, could you make the bank registers 16 bit and the address bus 32 bit?

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