I didn't want to hijack akohlbecker's thread about 65C816 computer YouTube series but I read about Andre's CS/A bus in recent posting that I'm interested in exploring more in a separate topic. I think bus with multiple chip selects for memory, dedicated I/O, mass storage, and general I/O has potential for compact design but what's the drawbacks?

I have my own decoded bus conceived a few months ago, and a design blog about it. Currently the CPU is Z80 but next processor for it will be 6502/65816.
Bill

Andre has a lot of interesting documented designs, I looked at this one a year or two ago when I was playing with hardware memory protection and per-process paging. I found it interesting that the processor module was just another module on the bus, rather than something built into the system, so it could easily allow different processors to be substituted, and even with the right arbitration, multiple processors present simultaneously. Maybe it's an obvious concept to people with more experience, but I'd always seen the CPU as the heart of the computer, and this turned that upside down for me.

Well, that's what I did back in 1987 as my MSc - a 16-bit modular microcomputer with 8086, MC68000 and (planned but not finished) Z8000. The system was capable of multiprocessor operation. Every CPU had its own ROM and there was a RAM board shared by all CPUs. 74188 PROM was used as programmable logic for address decoding.

There are two drawbacks I'm seeing: (though I'll follow this thread to see if someone thinks of things I missed)
- Increased number of signal lines needed in the bus, maybe not an issue if using large pin count connectors such as 96 position DIN41612 or 164 position PCIe.
- Need to determine the size of each card's dedicated I/O space beforehand, in the address decoding circuit, whereas a card that includes its own dip switch+comparator can be mapped to arbitrary sizes of memory.

I will probably go with a hybrid of what you're proposing in my own bus design:
I'll include decoded IO selects (8 or 16) for 16 bytes of addresses each in the bus. This way, mapping a card to I/O space can be done using only a jumper in a 2x8 header instead of the DIP+Comparator combo, which will be quite a lot faster in propagation times.
However, I'm thinking the board responsible for decoding the address map will also contain the RAM and ROM, in order to pack cards more densely, so I might not include memory selects

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BB816 Computer YouTube series

Thanks for the interest!

I habe actually built a number of CPU boards for the CS/A bus already. (With MMU and protection bits, a normal 6502 with ram/rom included, 8MHz 65816 board, and just recently the 12.5MHz 65816 Ultra-CPU board with included VGA output)

What I recently found intriguing was the geographical addressing of the Apple slots. It requires a specific backplane that I didn't have at that time when I designed it, but makes life so much easier without address jumpers on the boards and driver autodetection

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/