Following on from this post I've tried detecting interrupts BEFORE any of the stack pushes occur; and using Dr Jefyll's schematic below

I've simulated up the following for detecting software interrupts:
and hardware interrupts:
And both cases seem to work quite nicely. Excellent!


I have made a change to the latching logic to only latch the opcode when PHI2 is high and VDA and VPA are also both high. It might be overkill but if I ever have a need to know the opcode I'll have it sitting in that latch.

I've changed the '574 to a '573 because the '574 is a chonky boi. The SO20 takes up a LOT of space whereas the '573 is available as a TSSOP20.

I'm using a pair of comparators for a couple of reasons firstly I don't want to have to muck around with a bunch of NAND gates and inverters each of which cost the same as the comparator and secondly it makes testing for other opcodes much easier. I'll probably also swap the 'F521 for an 'HC688 (because again, the 'F521 is another chonky boi) but this is all still simulation land.

I've separated the circuits into hardware and software to make it easier for me to understand but ultimately to add hardware interrupt detection into the software circuit only needs a single NOR gate.

And that's a big thank you to everyone on this forum for the help. It's very much appreciated

(and after all of this I've realised I may have a problem switch back to user mode on the RTI leg ... but that's a problem for another time)

Bravo!

Glad to hear the info I provided has been helpful.

It's worth noting the same scheme works for '02 and 'C02 processors. The only difference is trivial: with the '816 you need a gate to determine which cycles are opcode fetches. On '02 and 'C02 you can simply use SYNC.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

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Got a kilobyte lying fallow in your 65xx's memory map? Sprinkle some VTL02C on it and see how it grows on you!

Mike B. (about me) (learning how to github)

Ta!


Very thanks! I've added a bit to the original design since.

I also needed to detect when an RTI was done using the stack so I've added a '595 shift register to count the cycles of said RTI. Its working well in simulation and hopefully I should be getting to building things in the real world soon (after payday )
A one gets shifted into the shift register whilst the op-code is an RTI and VDA & VPA. When Q5 on the shift register goes high then I know it's on the sixth cycle of the RTI and it's done with stack manipulation*.

After that things get a bit implementation specific but I count up on interrupts (both hardware and software) and count down on return from interrupts.
Yes, I am using a '521 to check for zero . It's cheaper and smaller than any other combination of ICs I can find unless there's an eight input NOR gate I haven't found.

In simulation RESET is being detected as an interrupt which starts the counter at one. I'm hoping this will work because I want to start at one in kernal mode.

*In native mode, I think emulation mode would be the 5th cycle.