RTI behaving strangely

[Synthron]

Hey everyone,

I'm currently at a loss.... I try to test and play with interrupts, which btw work as intended, but the RTI instruction is behaving strange...

As soon as I try to RTI, the processor is reading the wrong return address and just randomly jumps anywhere... I logged it and at Interrupt he pushed address $801A into stack, at RTI he pulled $1A1A from stack, landing somewhere in not initialized RAM and just spasms out of control...

anyone here can help?

It both happens at NMI and IRQ, RTS is working just fine, exceot when I try to RTS from the interrupt... I have no Idea what to do...

[BigEd]

With what system is this? And how are you logging addresses?

[Synthron]

on my own SBC I posted a while back (didn't have much time since then but now I'm tackling it again), see viewtopic.php?f=12&t=6513

I also tried to do something different. basically I tried to RTI to a specific address with the following:

Code: Select all

lda #$80
pha
lda #$20
pha
php
rti

with the first instruction located at $8020 thus creating a loop (checked it in the hex file)
interestingly enough this works perfectly fine, so now I am wondering...

I tried the minimal example of

Code: Select all

ISR:
    rti

which again resulted in wildly different random address accesses...

[GARTHWILSON]

Since $1A is one of the address bytes and the $80 is lost, it kind of sounds like your ISR is not balancing the stack.

[Synthron]

GARTHWILSON wrote:

Since $1A is one of the address bytes and the $80 is lost, it kind of sounds like your ISR is not balancing the stack.

then again, why did the manual approach work?

[GARTHWILSON]

Can you post your ISR code.

[Synthron]

ok, found something out... after back-checking with the 6502-primer here I noticed that /WE should be qualified by Phi2, so that on Phi2=low no write operation would be possible...
I hacked together a small logic circuit out of 2 NAND gates which are first inverting R/W from the 6502 and then NANDing it with Phi2. on slower clock-speeds this works perfectly well, at 1MHz the VIA doesn't issue the IRQ from the button... sooo... something is wrong with the VIA I guess?

Manual triggering of the IRQ-line works as expected now, so consider the problem solved

[GARTHWILSON]

The WR\ to the memory needs to be separate from the signal to the VIA. Make sure you're observing that. The VIA needs the RS and R/W lines to be valid and stable before the rise of phase 2. I have never seen a VIA come defective when new, even though we used them for 13 years in one of our products. The possible exception, if I'm remembering correctly, was one where a bond wire on one of the port pins seems to have let go after it was in the field for awhile in heavy vibration. Apparently the bond was good enough to get it through initial testing, but not good enough to last.

[Synthron]

will have a look at that later,

for now I switched the WDC 65C22S for a Rockwell R65C22P and added a pullup-resistor at the /IRQ-Pin, now it works flawlessly, even at higher clockrate

and thanks Wilson for the primer, should've read it more thorough before designing the pcb ^^

[BigDumbDinosaur]

From your other topic:

Quote:

0000 - 3FFF = Banked RAM

Why? Banking that range means the stack, among other things. I'll let you figure out the implications.

[Synthron]

BigDumbDinosaur wrote:

From your other topic:

Quote:

0000 - 3FFF = Banked RAM

Why? Banking that range means the stack, among other things. I'll let you figure out the implications.

I know that it is unusual and can be complicated, I had my reasons for that and still have to implement these reasons

[Synthron]

GARTHWILSON wrote:

The WR\ to the memory needs to be separate from the signal to the VIA. Make sure you're observing that. The VIA needs the RS and R/W lines to be valid and stable before the rise of phase 2. I have never seen a VIA come defective when new, even though we used them for 13 years in one of our products. The possible exception, if I'm remembering correctly, was one where a bond wire on one of the port pins seems to have let go after it was in the field for awhile in heavy vibration. Apparently the bond was good enough to get it through initial testing, but not good enough to last.

the R/W for the VIA is untouched. I lifted the /WE pin of the RAM off the board and soldered the gates directly to it. R/W for the VIA still is normal R/W