Zero glue logic 6502 SBC?

[fachat]

Michael wrote:

As for zero glue logic... If I replace the ROM chip with a boot loader / rom emulator chip on a 64K RAM design, might that be worth an "atta boy"?

For me that defeats the purpose of the 6502 ... a support chip that is even more powerful than the 6502....

But I used a CPLD to copy over some boot code from an SPI Flash to RAM, what about this?

André

[plasmo]

Reviving this thread about a zero glue 6502 because I thought of a way to cascade reset supervisor and that solved the problem of enabling EPROM at power/reset without glue logic.

Here is a no glue 6502 design. A normal 6502 SBC with 32K RAM at 0-7FFF, ACIA at 8000-BFFF, and EPROM at C000-FFFF. The only unusual circuitry is two MCP130 reset supervisors cascaded so first MCP130 reset 6502 and 2nd MCP130 which controls EPROM chip_select. After 6502 reset is negated, the EPROM remains enabled for another 350mS, nominal. During that time 6502 copies program from EPROM to RAM and then jumps to RAM. The EPROM then goes offline after 350mS. I added two expansion slots because the EPROM memory area (C000-FFFF) can be recycled for other I/O devices as long as it does not respond to the initial 350mS enabling pulse.

I'll layout the board and have it ready for next time when I'm sending out a batch of pcb.
Bill

[Michael]

plasmo (Bill) wrote:

Here is a no glue 6502 design.

Hi Bill.

After reset and 350-ms, is there anything in the $C000..$FFFF address space to vector an IRQ request?

[plasmo]

Argh! the devil is in the detail. No, I have not thought about interrupt vector. I'll probably provide pull up/down resistors and force interrupt to, say, 0x0202. Thanks for thinking of it.
Bill

[hoglet]

plasmo wrote:

Argh! the devil is in the detail. No, I have not thought about interrupt vector. I'll probably provide pull up/down resistors and force interrupt to, say, 0x0202.

You might be able to use the W65C02 VPB output to re-enable the ROM.

You would need to diode-OR VPB with the output of the second MCP130.

[Michael]

Well... Playing devil's advocate... If you can use an MCP130 the way you are without calling it "glue", couldn't you use a pair of diodes, a transistor, and a couple pull-ups to leave ROM in memory space at $C000..$FFFF? I suppose it depends on what you consider "glue", yes, no?

[plasmo]

VPB is an excellent idea!

My twisted logic about "No glue" is this: Since I'm already using one MCP130 as the voltage supervisor and convinced myself I've not "sinned", surely 2nd MCP130 is still all right--at least that's my reasoning. The alternative is two push switches, push both down, release one to run 6502, then release the 2nd to remove EPROM. Yike! that's just ugly.

The EPROM actually occupies the entire memory space when it is enabled during the 350mS period. I can copy it to RAM (residing in 0x0-7FFF) even though both EPROM and RAM are enabled because it is a write operation. Once RAM has same values as EPROM, I can also jump into RAM and execute without data contention because EPROM and RAM contents are the same, but I can not access I/O until EPROM has removed itself from the memory map.
Bill

[Michael]

Kinda' reminds me of the John Bell Engineering 82-300 board...

[BillO]

Michael wrote:

Kinda' reminds me of the John Bell Engineering 82-300 board...

That 2N2222 kinda looks like a tiny spot of glue. 3 chips and a transistor ain't bad though.

[Michael]

BillO wrote:

Michael wrote:

Kinda' reminds me of the John Bell Engineering 82-300 board...

That 2N2222 kinda looks like a tiny spot of glue. 3 chips and a transistor ain't bad though.

I wonder what that extra MCP130 in plasmo's design looks like to you, Bill?

[BillO]

Michael wrote:

I wonder what that extra MCP130 in plasmo's design looks like to you, Bill?

Maybe just a sticky little sin. Certainly not mortal, but ..

A few years back I was working on a design along these lines. I got it down to 4 chips (6502, RAM, ROM, 6551) but I used an oscillator (some would call this a chip), several diodes and 2 MOSFETs.

The diodes and MOSFETs were definitely quite "sticky". I got it working at low speeds but, like vegetable chop suey, it was not really satisfying.

[plasmo]

I need more than an inverting transistor because EPROM needs to be disabled and tri-stated after its content is copied to RAM otherwise the whole system is just one big EPROM.

Because there is no glue logic, I speculate the board can run quite fast with appropriately fast EPROM and RAM, even though W65C51 is spec-ed at 4MHz, I suspect it can run much much faster.
Bill

[GARTHWILSON]

plasmo wrote:

even though W65C51 is spec-ed at 4MHz, I suspect it can run much much faster.

https://wdc65xx.com/integrated-circuit says "14 MHz Operating Bus Speed" even though the data sheets I have for it (the latest being six years old) didn't reflect that yet.

[plasmo]

I have ordered a few W65C51 and I just now noticed the part number is W65C51N6TPG-14 which the WDC datasheet says can run at 14MHz but provides no AC characteristics (only 2MHz and 4MHz timings are provided). Hmmm, with 45nS W27C512-45Z EPROM, I probably can run the board to 25MHz.
Bill

[plasmo]

The 6502 ROM-less programmer board turns out to be a good prototype board for other projects. I used it to prototype the zero-glue 6502 SBC by adding a W65C51 and 2nd reset supervisor in the prototype area. The manual wiring is reasonable since most connections between CPU/RAM/ROM are already on the pc board.

I wrote a small boot software that copies a program from EPROM to RAM, spin in RAM until EPROM's chip select is negated by the 2nd reset supervisor (about 350mS), and then write test data out to the serial port. It all works pretty well.
Bill