Ok, simple question which I haven't been able to find an answer for anywhere.
How many transistors is the 65c816? Or alternatively the die size.
How many transistors is the 65c816?
The die size can be found in patent 4739475 (if you download the pdf you also see some chip-scale layout.)
The hope, it seems, was that 65816 would be half the size of competing 16-bit micros.
If you like a good story, or want some insight into the transistor-level layout-centric approach taken, have a read of the patent. Here's an illustrative snippet:
"As this approach to layout of the sum-of-minterm region 116B progressed, my foregoing hunch turned out to be correct, and with much less effort than I thought might have been required, I was able to complete the layout of the sum-of-minterm region with much less expenditure of time, and with only approximately 40% less chip area than I thought would have been required if I had not hit upon this approach"
Several of WDM's 'topography' patents read like this- quite unlike other patents I've read.
The hope, it seems, was that 65816 would be half the size of competing 16-bit micros.
If you like a good story, or want some insight into the transistor-level layout-centric approach taken, have a read of the patent. Here's an illustrative snippet:
"As this approach to layout of the sum-of-minterm region 116B progressed, my foregoing hunch turned out to be correct, and with much less effort than I thought might have been required, I was able to complete the layout of the sum-of-minterm region with much less expenditure of time, and with only approximately 40% less chip area than I thought would have been required if I had not hit upon this approach"
Several of WDM's 'topography' patents read like this- quite unlike other patents I've read.
From that patent: die size is 278x164 mils (25.4 microns per mil). Also some internal driver transistors are sized at 9micron gate width, and some poly lines are given as 5micron wide. Sounds like the process has an approx 7 micron metal pitch.
The described chip uses precharged logic techniques, which will mean fewer transistors are needed for a given logic function. In particular, the main decode array which dominates the chip is NMOS only. So transistor counts and equivalent gate counts won't bear much relation to other implementation technologies.
Of course, the patent won't reflect current production process or die size. I see Garth previously found a reference to WDC using a 0.8u process.
Although the patent text says that full chip layouts are included as diagrams, they are absent from the pdf version. (They are present in patent 5123107 which is a 65c02-based microcontroller wsc65c134s, and for 4652992 which is the 65c02, and also for Buchanan's 3987418 which looks like a 6800)
The described chip uses precharged logic techniques, which will mean fewer transistors are needed for a given logic function. In particular, the main decode array which dominates the chip is NMOS only. So transistor counts and equivalent gate counts won't bear much relation to other implementation technologies.
Of course, the patent won't reflect current production process or die size. I see Garth previously found a reference to WDC using a 0.8u process.
Although the patent text says that full chip layouts are included as diagrams, they are absent from the pdf version. (They are present in patent 5123107 which is a 65c02-based microcontroller wsc65c134s, and for 4652992 which is the 65c02, and also for Buchanan's 3987418 which looks like a 6800)
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Re: How many transistors is the 65c816?
According to https://en.wikipedia.org/wiki/Transistor_count, the '816 has 22,000 transistors, and the 65c02 has 11,500.
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?