Thinking about the small CPLD bootstrap code in CRC65, it occurs to me that manually toggle in 6502 opcode may not be too bad of a solution for the simple EPROM programmer. We know all about manually entering the opcode on the front panel, but the difference here is there are no switches for addresses. I'm relying on 6502 to generate the addresses and write the manually entered opcode into RAM at the appropriate addresses while 6502 is also executing the manually entered instruction. Here is a trial balloon design:
W65C02
RAM at 0x9000-0xFFFF
6551 at 0x8000-0x8FFF
EPROM at 0x0-0x7FFF <-- Yes, I know page zero is in EPROM, but hear me out...
1.8432MHz clock
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8 switches on data bus to force data high or low,
switch to disable RAM output enable and enable RAM write enable
debounced switch to single step clock
reset switch
At first power, RAM is set to write always, but its output enable is disabled; clock is driven with debounced single step switch. This is the program I want to manually enter:
Code:
0x00 ;reset vector low
0x90 ;reset vector high
LDX #0
chkRDRF:
LDA ACIA_STATUS
AND #8 ;check ACIA Receive data full
BEQ chkRDRF
LDA ACIA_DATA
STA $9012,x
INX
BNE chkRDRF
This program loads 256 bytes of bootstrap starting from location 0x9012 which is at the end of this program
Once the program is manually entered, reset 6502, set RAM to normal, set clock to 1.8432MHz and release reset. 6502 will execute the same sequence of instructions EXCEPT the branch instructions. There are two branches, 1), testing the serial data received full, and 2), X register equals 0. I can force the program to take serial data receive full branch by sending a serial data to ACIA while manually entering the opcode; I don't need to force the X register equals to 0 because that's the end of manually entered program and where the serially loaded program starts.
Why is EPROM locates in 0x0-0x7FFF? Because I don't want newbie to pay for the ridiculously expensive EEPROM when fast SST39SF010 is $1.50. Programming SST39SF010 requires address 0x2AAA and 0x5555 map to EPROM to enable software command sequences. Not having Zero page may mean self-modifying code for the EPROM programming software, however
By my count, 20 manual entries are needed, not too bad if it only need to be entered a few times, but the poor sucker who designed and debugged this (i.e., yours truly) will regret ever thought of this idea!
Bill
Edit:
Thinking it over, I see there are potential complexity due to some opcode may take more instruction cycles to execute before fetch next opcode. Depending on how messy that turned out, the fall-back method is separating RAM data bus from CPU data bus with a bidirectional buffer (74245) and pull CPU data bus to the NOP instruction value (0xEA), and change the bootstrap code starting location to 0xEAEA. So after reset 6502 fetches 0xEAEA as the reset vector and starts fetching instructions from 0xEAEA. 6502 will continue to execute NOP while the front panel switch values are written into successive locations of RAM. This takes extra buffer and 8 resistors, but is a more generic solution.