Could someone look this over?

Bramblefax · Post by **Bramblefax** » Thu Jul 30, 2009 9:13 pm

I'm new to micro design, so I was wondering if someone could give me some pointers about this schematic:
http://socialkonstrukt.com/hunley-1.GIF
The PT0-7 will be to a parallel receipt printer, DSP0-7 will go to this LCD display http://www.allelectronics.com/make-a-st ... GHT/1.html through a MAX233, and KB0-7 is to an ascii keyboard. The enable/strobe pins for these are all on one 6522 port together, so the printer and display can be strobed together. I know I'm wasting a lot of address space with the decoder setup, but that's OK with me for now.

Would this work? Is there some glaring or subtle design mistake I should fix before ordering the parts? Do I need to buffer the i/o? Am I missing something obvious?

GARTHWILSON · Post by **GARTHWILSON** » Thu Jul 30, 2009 10:24 pm

The processor's phase-1 input must be used for the clock circuit, whether you use the internal oscillator or not. Phase 2 on the 6502 is an output, not an input.

You'll need a RST circuit, even if it's just an RC. (The CMOS 6502 has a schmitt-trigger input there, and timing is not critical like it was on the NMOS 6502.) Take the RST line to the 6522's also. Don't leave their RST lines floating.

If you use a WDC 65c02, pin 1 is a VP (vector pull) output, so you won't want to ground that. If it's another brand, just leave it grounded.

The RAM's W\ line will have to go to the processor's R/W\ output.

You need to gate the RAM select with phase 2, because the address lines are not guaranteed to be valid before the R/W\ line is, let alone with enough set-up time for the RAM. Without gating RAM select with phase 2, you could inadvertently write to wrong addresses and corrupt your data. Don't gate everything with phase 2 though, as the 6522's need the chip-select lines to be valid and stable before phase 2 rises. The address decoding for much more than this can be done with a single 74xx00, and allow faster running too. See http://www.6502.org/users/garth/project ... chematic=2 . (Replace the inverter with a section of the 74xx00.)

You need the 3.3K pull-up resistor on the IRQ line. If you use WDC's 65c22's which have totem-pole IRQ\ outputs, you'll have to AND them together and feed the output of the AND gate to the IRQ\ input of the processor.

Don't leave the processor's NMI, RDY, and S.O. inputs floating. Tie them high.

The MAX233 won't be of any value feeding the LCD which, according to the data sheet, only has a 4- and 8-bit parallel interface with TTL levels, not RS-232 levels.

When you get ready to write the software for the LCD, contact me, as there's a trick to getting a dependable reset on it.

If you wanted to, you could make the same 8 data lines to feed the LCD and the printer and the keyboard, then use the other port of the same 6522 for the handshake and select lines.

This was very hastily written. I won't feel bad at all if someone points out things I missed!

Bramblefax · Post by **Bramblefax** » Fri Jul 31, 2009 3:23 am

Quote:

The processor's phase-1 input must be used for the clock circuit, whether you use the internal oscillator or not. Phase 2 on the 6502 is an output, not an input.

I think I understand what you mean here. I have the canned oscillator going straight into phase-1 now.

Quote:

You'll need a RST circuit, even if it's just an RC. (The CMOS 6502 has a schmitt-trigger input there, and timing is not critical like it was on the NMOS 6502.) Take the RST line to the 6522's also. Don't leave their RST lines floating.

I'm using a MAX706 here. I'm ignoring the watchdog timer. Do you think that will be OK?

Quote:

If you use a WDC 65c02, pin 1 is a VP (vector pull) output, so you won't want to ground that. If it's another brand, just leave it grounded.

It's a Rockwell, I think.

Quote:

The RAM's W\ line will have to go to the processor's R/W\ output.

fixed.

Quote:

You need to gate the RAM select with phase 2, because the address lines are not guaranteed to be valid before the R/W\ line is, let alone with enough set-up time for the RAM. Without gating RAM select with phase 2, you could inadvertently write to wrong addresses and corrupt your data. Don't gate everything with phase 2 though, as the 6522's need the chip-select lines to be valid and stable before phase 2 rises. The address decoding for much more than this can be done with a single 74xx00, and allow faster running too. See http://www.6502.org/users/garth/project ... chematic=2 . (Replace the inverter with a section of the 74xx00.)

Thank you very much for this circuit. It's much more elegant. I'm also upping my RAM up to 16k like your bench computer. It's only a few pennies more.

Quote:

You need the 3.3K pull-up resistor on the IRQ line.

Fixed. Stupid mistake. Thanks!

Quote:

Don't leave the processor's NMI, RDY, and S.O. inputs floating. Tie them high.

More noobishness on my part. Thanks

Quote:

The MAX233 won't be of any value feeding the LCD which, according to the data sheet, only has a 4- and 8-bit parallel interface with TTL levels, not RS-232 levels.

Yeah, I don't know what I was thinking.

Quote:

When you get ready to write the software for the LCD, contact me, as there's a trick to getting a dependable reset on it.

I'm curious to know now

Quote:

If you wanted to, you could make the same 8 data lines to feed the LCD and the printer and the keyboard, then use the other port of the same 6522 for the handshake and select lines.

You're right, that would be much more clever. I'll ponder this while I'm painting my kitchen this weekend.

Quote:

This was very hastily written. I won't feel bad at all if someone points out things I missed!

Thank you very much. These were most helpful.
EDIT: Here's the revised schematic: http://socialkonstrukt.com/hunley-6502-rev2.GIF. Does anyone else see anything wrong with the design? I would really appreciate the help. Also, does anyone know where I can source a parallel ascii keyboard?
EDIT2: pretend that the 2865 eeprom is a 32k device.

GARTHWILSON · Post by **GARTHWILSON** » Fri Jul 31, 2009 7:18 am

Quote:

I'm using a MAX706 here. I'm ignoring the watchdog timer. Do you think that will be OK?

I'm sure it will be fine, but it might be easier to do something like in http://www.6502.org/users/garth/project ... chematic=1 .

Quote:

EDIT: Here's the revised schematic: http://socialkonstrukt.com/hunley-6502-rev2.GIF.

I get an error 404 (page not found) on that one.

For a keyboard with the matrix interface brought out, there are probably a lot of vintage computers you could get one from.

8BIT · Post by **8BIT** » Fri Jul 31, 2009 2:35 pm

I'll through in a few items:

I'm not sure you can tie the outputs of the 74138 together to create the /CS for the RAM. You can use A15 as the /CS for the RAM. That gives you 32k of RAM space.

Also, you cannot connect the /CS and /OE together on the RAM. The /OE will need to have an inverted CPU R/W as it input. Otherwise, during a write cycle, both /OE and /WR would be active.

I'll check over your revised schematic, once its posted correctly.

Daryl

Bramblefax · Post by **Bramblefax** » Fri Jul 31, 2009 3:58 pm

SORRY!
http://socialkonstrukt.com/hunley-2.gif
That should work. Thanks guys.

leeeeee · Post by **leeeeee** » Fri Jul 31, 2009 6:02 pm

Quote:

Also, you cannot connect the /CS and /OE together on the RAM. The /OE will need to have an inverted CPU R/W as it input. Otherwise, during a write cycle, both /OE and /WR would be active.

Yes you can as /OE is justified internally with /CE and //WE. It is even specifically allowed in most static RAM data sheets.

You can, if you wish, hold /OE permamently low to no ill effect in most cases.

Lee.

Bramblefax · Post by **Bramblefax** » Sat Aug 01, 2009 9:14 pm

Garth, you said you have some experience with this type of lcd. If I'm running at 1mhz, would it be better to hang it off a VIA, or to put it straight on the bus. I ask because I'm digging through the datasheets, and it seems like the programming will be greatly simplified if it's directly on the bus. If so, do you have any tips for doing so?

GARTHWILSON · Post by **GARTHWILSON** » Sun Aug 02, 2009 6:20 am

If you don't think you'll ever exceed 1MHz, you definitely can hang it on the bus. I would evaluate the difference in hardware to see which way makes for fewer parts. (Note that the LCD has an enable line, not an enable-not line.) The RS line can be connected to an address line. I've used these many times and I don't think I've ever read from them-- only written to them.

The data sheets of the ones I've used show that you couldn't expect them to work much over a MHz, but at 1MHz you can get away with murder. The common newbie construction errors aren't nearly as likely to keep the home-made computer from working, as long as the parts' speed is held down too instead of just the clock speed. What kills is the fast rise times, not particularly the clock speed. If you had fast parts but clocked them at a low speed, you could still have problems; but I don't think Rockwell ever sold any 65c02's that were rated for more than 4MHz, and you can use 74HC logic with that just fine. WDC's will all do at least 16MHz, and they justify 74AC or ACT logic which is much faster.

Bramblefax · Post by **Bramblefax** » Mon Aug 03, 2009 2:22 am

GARTHWILSON wrote:

I've used these many times and I don't think I've ever read from them-- only written to them.

What do you do about the busy flag? just do your own timing to figure out when it should be free again?

8BIT · Post by **8BIT** » Mon Aug 03, 2009 2:48 am

leeeeee wrote:

Quote:

Also, you cannot connect the /CS and /OE together on the RAM. The /OE will need to have an inverted CPU R/W as it input. Otherwise, during a write cycle, both /OE and /WR would be active.

Yes you can as /OE is justified internally with /CE and //WE. It is even specifically allowed in most static RAM data sheets.

You can, if you wish, hold /OE permamently low to no ill effect in most cases.

Lee.

I stand corrected. I should have read the datasheet before I spoke.

Thanks for keeping me honest, Lee!

Daryl

Bramblefax · Post by **Bramblefax** » Mon Aug 03, 2009 3:11 am

Another question: Why, in Garth's 74x00 address decoder, does the RAM need to be gated with phase2, but the ROM doesn't?

GARTHWILSON · Post by **GARTHWILSON** » Mon Aug 03, 2009 4:48 am

Because the address lines are not valid and stable for the necessary set-up time before the R/W\ line goes down, meaning that you can write to invalid addresses and corrupt whatever data was there if you let the RAM go ahead before phase 2 goes up. At the other end, after phase 2 goes down, there's no guarantee that the data and address lines will all remain valid until after the necessary hold time after R/W\ goes back up. OTOH with ROM, there's no danger of storing garbage to any address on it and corrupting it, since it's read-only.

This is #22 of my "Tip of the Day" column at viewtopic.php?t=342&start=22 .

Bramblefax · Post by **Bramblefax** » Mon Aug 03, 2009 6:58 am

Garth, could you shed some light on my previous question. Specifically, if you never read from the display, how do you ascertain whether its busy or ready to accept input?

GARTHWILSON · Post by **GARTHWILSON** » Mon Aug 03, 2009 7:28 am

The data sheet gives you the maximum amount of time that any given operation will take. If you just delay that amount of time before writing again, you'll be fine. I was never writing to such big displays that the delays were an issue. The biggest I've used was 40x4, and that's really two 40x2's stacked, so I think you could even write to one, then to the other while the first one is processing the instruction or data, then go back to the first, and so on, to make it go faster if you needed to completely re-fill the screen in the shortest possible time (even though you could go much slower without any visible delay).