B36502X Single Board Computer

[ThePhysicist]

I had a DS1813 working for about 2 months in my SBC and suddenly it died - maybe something similar happened here?

[Dr Jefyll]

Individual_Solid wrote:

It all works. [...] this revision has fully come to life.

Wow -- really? I'm glad, of course. But you seemed to have some pretty strange glitches on SYNC. These could perhaps be an artifact of your 'scope setup, and have no functional implications. But unless these can be explained I'm left with a nagging feeling that all is not yet well.

-- Jeff

[Individual_Solid]

Dr Jefyll wrote:

Individual_Solid wrote:

It all works. [...] this revision has fully come to life.

Wow -- really? I'm glad, of course. But you seemed to have some pretty strange glitches on SYNC. These could perhaps be an artifact of your 'scope setup, and have no functional implications. But unless these can be eliminated or at least explained I'm left with a nagging feeling that all is not yet well.

-- Jeff

I think that weirdness (at least, in the second screenshot you posted) comes from the CPU starting up and then being pulled back into RESET.

I just took some shots of a trace with the now functioning RESET circuit.

This is showing mostly NOPs with an occasional register decrement. This is a little noisy, but I'm definitely attaching the probe grounds a little far from the signal source. Do you still see something I should be worried about? I can do a trace from power-on again, if that's worth while.

[Dr Jefyll]

No, I don't notice any problem with these latest traces. SYNC should go high for one entire cycle at a time -- never a fraction of one cycle. And yet, fractional-cycle glitches is what the previous traces seemed to show.

-- Jeff

[Individual_Solid]

Dr Jefyll wrote:

No, I don't notice any problem with these latest traces. SYNC should go high for one entire cycle at a time -- never a fraction of one cycle. And yet, fractional-cycle glitches is what the previous traces seemed to show.

Thanks for double checking for me! I'm getting pretty quick at setting up these experiments on the scope!

[BigDumbDinosaur]

Individual_Solid wrote:

Dr Jefyll wrote:

No, I don't notice any problem with these latest traces. SYNC should go high for one entire cycle at a time -- never a fraction of one cycle. And yet, fractional-cycle glitches is what the previous traces seemed to show.

Thanks for double checking for me! I'm getting pretty quick at setting up these experiments on the scope!

Just for grins, try inserting some series resistance into the clock circuit to see if you can dampen some of the over-/undershoot in the signal. The degree of over-/undershoot shouldn't be detrimental to your application, but dampening it may also reduce noise in other places.

If you try this, place the resistor as close to the clock source as you can. I'd start at 100 ohms. BTW, you're likely to see better results with a metal film resistor than a carbon one.

[Individual_Solid]

After a lot of thinking, I am pretty convinced I am going to switch the expansion connector from 1x40 to 2x25. I wrote up the new bus layout over here: https://github.com/Individual-Solid/f1m ... /s50Bus.md. A majority of the differences from the 1x40 pinout are...more ground lines! And only two unassigned signal lines, since I decided to put SYNC/RDY/ML/BE all on the bus.

It means a lot of redesign, but much easier to keep the board down to 102x102mm and the connections are mechanically much more secure than the 1x40.

I'm interested in adding clock stretching circuit where an expansion card could request the CPU get a slow clock (while the VIAs and any expansions would still have PHI2 as their main system clock).

Any bus feedback? Otherwise, I'll be back with more drawings soon!

[Individual_Solid]

Realizing I don't have a good idea of how to draw a schematic in KiCad that uses either a 30 or 32 pin storage device. I appreciate the pinout diagram that kernelthread posted, and I have an idea of how I'd lay out the traces if I was just doing a PCB layout, but I'd like to actually capture and document the circuit. I'll probably use a hierarchical page off of the main page that breaks out to show BOTH rom devices, set up the jumpers, and then overlap them on the pcb? I'm just not sure. I'll look around for some tutorials on KiCad that discuss something like this.

[jds]

Individual_Solid wrote:

Realizing I don't have a good idea of how to draw a schematic in KiCad that uses either a 30 or 32 pin storage device. I appreciate the pinout diagram that kernelthread posted, and I have an idea of how I'd lay out the traces if I was just doing a PCB layout, but I'd like to actually capture and document the circuit. I'll probably use a hierarchical page off of the main page that breaks out to show BOTH rom devices, set up the jumpers, and then overlap them on the pcb? I'm just not sure. I'll look around for some tutorials on KiCad that discuss something like this.

The simplest option is to just use the 32-pin symbol. If you want it to be better documented than that, you could create your own symbol and label the pins accordingly. It would mostly look like the 32-pin device with some pins with double labels. I did this for a socket that could accept either a 65C02 or 65C816, which is a bit more complex than your memory case. I labelled pins that differed in function with labels like NC_VPB (pin 2), with the 65C02 label on the left and 65C816 on the right. Another example is pin 43 (PLCC) PHI2_VDA. I used 0 ohm resistors (or pull-ups in some cases) to connect the correct signals for each option, but jumpers are another way to do it.

[Alarm Siren]

An aside, and apologies for reopening the topic (I don't check this forum very often these days: lack of time ) but I noticed you're using the 6502-kicad-library I made a few years ago in your schematic, which makes me happy. I hope you found it useful, and best of luck with the project, it is looking good!