Phi2 produces instability

[gfoot]

Isn't this what priority encoders are for? I've never used them but I thought the idea was that you feed all your interrupt sources in, it provides an IRQ output, and you can also query it to find the lowest-numbered input that's low. Your ISR reads this, services that device, and returns; or loops if you like to service the next priority until there are none left.

[BillO]

floobydust wrote:

BillO wrote:

I've used software to manage multiple interrupts.

I took a brief look at your BIOS code, but I'm guessing it will take a lot more digging to interpret than the 10 minutes I've spent. So without some hardware, how do you determine which device requested the interrupt? Do you just poll them?

Edit:
A 74HCT148 and a 74AC245 might make a decent interrupt priority encoder that would work n a 6502 bus.

[floobydust]

BillO wrote:

floobydust wrote:

BillO wrote:

I've used software to manage multiple interrupts.

I took a brief look at your BIOS code, but I'm guessing it will take a lot more digging to interpret than the 10 minutes I've spent. So without some hardware, how do you determine which device requested the interrupt? Do you just poll them?

Yes, there is a core set of routines... one that handles each hardware device. They are linked through a vector table in page $03, so you can insert and change the sequence easily. Here's basic polling routine for the UART. Depending on what caused the interrupt, it branches to the routine that handles that.... if the UART did not trigger the interrupt, it exits quickly to the next handler, etc.

Code: Select all

;IRQ Vector defaults to here, which is the Start of Interrupt handler.
; NOTE: 25 clock cycles to get to this routine
; NOTE: If this ISR is after the IDE ISR, it will take 33 additional clock cycles
;
INTERUPT0                               ;Interrupt 0 to handle the SCC2691 UART
                LDA     UART_ISR        ;Get the UART Interrupt Status Register (4)
                CMP     #%00100000      ;Check for no active IRQ source (2)
                BEQ     REGEXT0         ;If no bits are set, exit handler (2/3)
;
                BIT     #%00001000      ;Test for Delta Break (2)
                BNE     UART_BRK        ;If yes, Reset the UART receiver (2/3)
                BIT     #%00000100      ;Test for RHR having data (2)
                BNE     UART_RCV        ;If yes, put the data in the buffer (2/3)
                BIT     #%00000001      ;Test for THR ready to receive data (2)
                BNE     UART_XMT        ;If yes, get data from buffer (2/3)
                BIT     #%00010000      ;Test for Counter ready (RTC) (2)
                BNE     UART_RTC        ;If yes, go increment RTC variables (2/3)
;
IRQEXT0         STA     UART_IRT        ;Else, save the 2691 IRT for later use (4)
                LDA     UART_STATUS     ;Get 2691 Status Register (4)
BUFF_ERR        STA     UART_SRT        ;Save 2691 Status Register for later use (4)
REGEXT0         JMP     (IRQRTVEC0)     ;Return to Exit/ROM IRQ handler (6)
UART_BRK        JMP     UART_BRK0       ;Gotta JUMP to the routine
;

The REGEXT0 does an indirect JMP to a vector located on Page $03, which can point to the next interrupt handler or the exit routine in ROM which restores registers, etc. and exits via RTI. Also note that the IRQ get handled in BIOS to determine BRK or IRQ and does an indirect JMP to a vector in Page $03 to the appropriate handler.

Code: Select all

;
IRQ_VECTOR                              ;This is the ROM start for the BRK/IRQ handler
                PHA                     ;Save A Reg (3)
                PHX                     ;Save X Reg (3)
                PHY                     ;Save Y Reg (3)
                TSX                     ;Get Stack pointer (2)
                LDA     $0100+4,X       ;Get Status Register (4)
                AND     #$10            ;Mask for BRK bit set (2)
                BNE     DO_BRK          ;If set, handle BRK (2/3)
                JMP     (IRQVEC0)       ;Jump to Soft vectored IRQ Handler (6)
DO_BRK          JMP     (BRKVEC0)       ;Jump to Soft vectored BRK Handler (6)
NMI_ROM         JMP     (NMIVEC0)       ;Jump to Soft vectored NMI handler (6)
;
;This is the standard return for the IRQ/BRK handler routines
;
IRQ_EXIT0       PLY                     ;Restore Y Reg (4)
                PLX                     ;Restore X Reg (4)
                PLA                     ;Restore A Reg (4)
                RTI                     ;Return from IRQ/BRK routine (6)
;

[GARTHWILSON]

This is getting off the topic of the phase-2 thing, although the original post (from fredericsegard) does mention interrupts, so I'll bite. It'd be good to have another topic about it if we continue to discuss them though, or tack onto the end of another one that's already discussing the same thing.

There are several ways to determine which source(s) caused the interrupt. Hardware that prioritizes them can only go so far though; because for example the 6522 VIA has seven possible interrupt sources, but only one IRQ\ output, meaning that once you know which VIA caused the interrupt, you still have to poll its status register to find out which source within the VIA did it. OTOH, there's no sense in polling for interrupt sources that aren't even enabled. On my workbench computer, I have, among the three VIAs and three ACIAs, 33 possible sources; but very few are enabled at any one time— most of the time only one on NMI and one on IRQ, making it easy. I never use BRK either. Most of the code I see in books or online for polling are very inefficient, polling everything even though most sources are not enabled. My favorite thing is to have routines to install, prioritize, and deactivate ISRs, although that borders on self-modifying code, something which is a little beyond the scope of my 6502 interrupts primer.

[ekrzycki]

Regarding PH2 clk - I ran into an issue with a test fixture on select Rockwell CPUs. The PH2 clk did not match the data book timing in a few cases. My first attempt at a test fixture many years ago worked for most CPUs but failed rather badly with a few CPUs that had no apparent problems.
Turns out the clock was skewed by quite a bit. I was qualifying the address, RdWr and PH2 clk for a quick and dirty latch. Sometimes the address & RdWr lines would be valid-ish during the undefined period and with the clock skewed - I got sporatic read/write values.
You can tell from this old timing drawing where the error popped in.

Had link to my website here but I forgot that I had 'hotlinking' blocked on my website so that didn't work.

[GARTHWILSON]

ekrzycki wrote:

OK... how do I insert an image?
For now you can find it here:
https://www.greatplainselectronics.com/ ... _ERROR.GIF

You did it right, but if I go to the URL, I just get the message, "You do not have permission to view this directory or page." Do you have to have an account and be logged in? What you could do is download the image, then attach it to your post.

We sold a product with a Rockwell 65c02 for 13 years using the phase-2-out and never had any problem. We would not be able to use the phase-2-in without using more parts though, because of the analog levels, as we were using just an RxC hung on the processor for controlling the clock speed, rather than an external oscillator.

[BigDumbDinosaur]

GARTHWILSON wrote:

ekrzycki wrote:

OK... how do I insert an image?
For now you can find it here:
https://www.greatplainselectronics.com/ ... _ERROR.GIF

You did it right, but if I go to the URL, I just get the message, "You do not have permission to view this directory or page."

I got the same thing.