ATF15xx Verilog/VHDL using Quartus 13.0 SP1
Re: ATF15xx Verilog/VHDL using Quartus 13.0 SP1
(Any chance of getting hold of and trying an older version of the converter?)
Re: ATF15xx Verilog/VHDL using Quartus 13.0 SP1
Martin A wrote:
I don't remember any errors being produced, but memory being what it is, I re-ran the conversion, and this is the log output:
Both versions produce the same JEDEC file, and so I guess if this issue is real, they both suffer from it.
There is a way to enable a detailed debug log to be generated from the command line version, and that suggests a problem right at the end of the POF file, where it tries to read the global clock bits, the JTAG bit and the User ID bits.
(and it seems to only happen when the 128-macro cell part is used)
BigEd wrote:
(Any chance of getting hold of and trying an older version of the converter?)
Dave
Re: ATF15xx Verilog/VHDL using Quartus 13.0 SP1
Quote:
The error is only visible (in the command prompt window) if you run the comand line version of the tool (POF2JED.exe) .
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kernelthread
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Re: ATF15xx Verilog/VHDL using Quartus 13.0 SP1
Sorry to revive an old thread, but I have just had a concrete instance of this problem. To be precise, I have a POF file, created from Verilog source using the Quartus 13.0-sp1 toolchain, which I can blow onto an EPM7128SLC84 obtained from ebay which works as expected. If however I run the POF file through pof2jed and blow the resulting JEDEC file onto an ATF1508AS, it doesn't quite work as expected. From the behaviour I reckon there are two differences in the actual logic implementation.
Does anyone here have any further information about this problem? What do people round here use to program their ATF1508's?
Does anyone here have any further information about this problem? What do people round here use to program their ATF1508's?
Re: ATF15xx Verilog/VHDL using Quartus 13.0 SP1
kernelthread wrote:
Does anyone here have any further information about this problem?
I think it might be connected with more complex use of clocks (i.e. a design that uses multiple clocks, or needs the clock inverting). From what I recall, the POF2JED tool was not correctly mapping the configuration of the global clock mux.
Dave
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kernelthread
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Re: ATF15xx Verilog/VHDL using Quartus 13.0 SP1
Yes, I can post the Verilog code. It's in the attached zip file. There are 3 Quartus projects in there - Test0, Test1 and Test2. Test0 is for the ATF1502, Test1 for the 1504 and Test2 for the 1508. They are intended to run on this board:
https://www.microchip.com/developmentto ... 15XX-DK3-U
These projects were produced to meet several aims - to help me get familiar with CPLDs and Verilog, to get some idea of how much stuff you can fit in one of these chips, to validate the programming setup and to test chips obtained from sources such as ebay.
The Test0 and Test1 projects work with no issues.
The Test2 project was not so fortunate. Basically the project consists of the following:
The system clock (2MHz on that board) is fed through three prescalers - first by 625 (down to 640Hz), second by 32 (down to 20Hz), third by a variable ratio from 1 to 16. The third prescaler output is fed to a two-digit BCD up/down counter. The board has 4 7-segment displays driven by 4 bit binary to 7-segment decoder modules, with each BCD digit driving two displays.
The push buttons are used as follows:
SW1 - changes between up and down counting
SW2 - increases prescaler 3 ratio (reduces count rate)
SW3 - decreases prescaler 3 ratio (increases count rate)
SW8 - pauses the count for as long as it is held
SW7 - switches the display between the BCD counter output and the prescaler 3 ratio and count.
What I found was that it all works on an EPM7128 device. If I use pof2jed and run the output on an ATF1508 I observe the following behaviour:
1. 7 segment display 3 displays the digit 2 incorrectly - the F segment is illuminated when it should not be. All other digits and all other displays work correctly.
2. When counting down, everything works correctly. When counting up, if the most significant digit is even it never changes; if it is odd, it increments when the least significant digit rolls over from 9 to 0, as expected.
There is only one clock in the system - the 2MHz clock provided by the on board xtal oscillator. Internally a low frequency clock is used to clock some stages, but that clock is obtained by dividing down the original 2MHz so there shouldn't be any timing or metastability issues.
The buttons drive the asynchronous reset pins of flip-flops used to implement debouncers.
https://www.microchip.com/developmentto ... 15XX-DK3-U
These projects were produced to meet several aims - to help me get familiar with CPLDs and Verilog, to get some idea of how much stuff you can fit in one of these chips, to validate the programming setup and to test chips obtained from sources such as ebay.
The Test0 and Test1 projects work with no issues.
The Test2 project was not so fortunate. Basically the project consists of the following:
The system clock (2MHz on that board) is fed through three prescalers - first by 625 (down to 640Hz), second by 32 (down to 20Hz), third by a variable ratio from 1 to 16. The third prescaler output is fed to a two-digit BCD up/down counter. The board has 4 7-segment displays driven by 4 bit binary to 7-segment decoder modules, with each BCD digit driving two displays.
The push buttons are used as follows:
SW1 - changes between up and down counting
SW2 - increases prescaler 3 ratio (reduces count rate)
SW3 - decreases prescaler 3 ratio (increases count rate)
SW8 - pauses the count for as long as it is held
SW7 - switches the display between the BCD counter output and the prescaler 3 ratio and count.
What I found was that it all works on an EPM7128 device. If I use pof2jed and run the output on an ATF1508 I observe the following behaviour:
1. 7 segment display 3 displays the digit 2 incorrectly - the F segment is illuminated when it should not be. All other digits and all other displays work correctly.
2. When counting down, everything works correctly. When counting up, if the most significant digit is even it never changes; if it is odd, it increments when the least significant digit rolls over from 9 to 0, as expected.
There is only one clock in the system - the 2MHz clock provided by the on board xtal oscillator. Internally a low frequency clock is used to clock some stages, but that clock is obtained by dividing down the original 2MHz so there shouldn't be any timing or metastability issues.
The buttons drive the asynchronous reset pins of flip-flops used to implement debouncers.
- Attachments
-
- PLDs.7z
- Verilog test projects for CPLDs
- (110.5 KiB) Downloaded 118 times
Re: ATF15xx Verilog/VHDL using Quartus 13.0 SP1
kernelthread wrote:
Internally a low frequency clock is used to clock some stages, but that clock is obtained by dividing down the original 2MHz so there shouldn't be any timing or metastability issues.
Let's say you have two flip-flops, with the output of A connected to the input of B, and both using the same clock. A's output will change slightly later than the clock edge, and by then B will have loaded A's previous output.
If B is using a derived clock, then its edges will come slightly after the one used by A. A's output might have already changed by the time B sees its clock edge. Or it might change later. Or it might change during the edge. You have no control over that.
Unless you must use multiple clocks (for example, you have an external device that provides one for communication), it's best to use one clock everywhere. Use the flip-flop's clock enable input to control when it loads.
Re: ATF15xx Verilog/VHDL using Quartus 13.0 SP1
kernelthread wrote:
Sorry to revive an old thread...
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kernelthread
- Posts: 166
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Re: ATF15xx Verilog/VHDL using Quartus 13.0 SP1
Another issue is that, even if I can get past this POF2JED problem, you have to start with a solution which fits on the EPM7128. Reading the data sheets, it seems that the ATF1508 has significantly increased functionality compared to the EPM7128, and lots of things which fit on the former won't fit on the latter. For example the 1508 has independent output enable lines on all I/O pins whereas the 7128 can only have 6 OE signals. You could implement a 6521/6821-style PIA on a 1508 with independent direction control of each line on a 1508, but not on a 7128. Also, the 1508 can, in some situations, use the flip flop in each macrocell independently of the I/O pin associated with it - the I/O can be driven by a combinatorial output while using the flipflop for buried logic.
I've been playing around with CUPL a bit since the first post. Wincupl is a hideous thing, with lots of crashes, although some can be avoided by using cupl.exe and find1508.exe from the command line rather than using the IDE. The CUPL language itself is horrible. It's very unpredictable - you never quite know what it is going to make of any particular construct. You can't use another macro from within a macro definition, which makes it quite hard to produce modular designs. In some cases the minimiser can crash if you use the maximum optimization mode (-m4).
One thought I have had is to use yosys to digest the verilog files and transform them into RTL. Then it might be possible to write a script which transforms the RTL into very simple CUPL code with no indexed variables or macros (the things which cause the unpredictable behaviour) and run that through the command line cupl compiler and fitter. Maybe that way I'll be able to use Verilog to program the 1508. Not much progress on this front so far, however.
I've been playing around with CUPL a bit since the first post. Wincupl is a hideous thing, with lots of crashes, although some can be avoided by using cupl.exe and find1508.exe from the command line rather than using the IDE. The CUPL language itself is horrible. It's very unpredictable - you never quite know what it is going to make of any particular construct. You can't use another macro from within a macro definition, which makes it quite hard to produce modular designs. In some cases the minimiser can crash if you use the maximum optimization mode (-m4).
One thought I have had is to use yosys to digest the verilog files and transform them into RTL. Then it might be possible to write a script which transforms the RTL into very simple CUPL code with no indexed variables or macros (the things which cause the unpredictable behaviour) and run that through the command line cupl compiler and fitter. Maybe that way I'll be able to use Verilog to program the 1508. Not much progress on this front so far, however.
Re: ATF15xx Verilog/VHDL using Quartus 13.0 SP1
Quote:
But I still get the error logged to the console:
Do you also see this error?
Code: Select all
***************************************************************
Error! POF Conversion may not be correct.
Please contact to Atmel EPLD Hotline (408)436-4333, or
email address (pld@atmel.com)
***************************************************************
I had carelessly picked an Altera device from the MAX7000AE series. Changing to a MAX7064SLC44 made this "maybe error" go away.
It remains to be seen whether the ATF1504AS-10JU44 is going to work with the produce .jed file.
Re: ATF15xx Verilog/VHDL using Quartus 13.0 SP1
Welcome, martingi, and good luck with the .jed file -- keep us posted, pls 
-- Jeff
-- Jeff
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html
https://laughtonelectronics.com/Arcana/ ... mmary.html
Re: ATF15xx Verilog/VHDL using Quartus 13.0 SP1
Thanks!
Still not done soldering all the wires onto that PLCC socket. But will let you know how it went!
Still not done soldering all the wires onto that PLCC socket. But will let you know how it went!
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BigDumbDinosaur
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- Contact:
Re: ATF15xx Verilog/VHDL using Quartus 13.0 SP1
I sort have been following this topic, as WinCUPL’s behavior can result in unproductive work and needlessly complicate the development cycle as I try to distinguish errors caused by my programming from errors caused by some obscure WinCUPL hiccup. However, it seems writing and compiling with Quartus, and then running its output through pof2jed results in a certain amount of, different, unproductive work as well. Then there is the fact that the Atmel CPLDs are more capable than their Altera equivalents.
So I rationalize my continued use of WinCUPL by telling myself that, yes, that environment can be un dolor real de huevos, as one might say in Spanish (PM me if you need the translation
), but less so than dealing with integrating two completely unrelated programs to produce something that may be used to program an Atmel CPLD. CUPL the language can be syntactically obstreperous, although I suppose the same could be said about other hardware development languages. I’ve learned the CUPL booby traps and mostly don’t have trouble with them. I’m still trying to understand the state machine stuff—it’s not explained well in the CUPL manual, something that I would eventually like to master.
In dealing with WinCUPL and its annoyances, treating the compiler and fitter as standalone programs seems better than running them from within the editor. Standalone operation is somewhat clumsy, although use of DOS batch files helps in that regard. Standalone execution has the distinct advantage of making error output from the compiler and fitter visible—normally such output is buried by the GUI. I have found the fitter’s unexpurgated error output to be useful in resolving obscure fit problems.
I have been doing my source editing in UltraEdit, which is a far better editor that that integrated into WinCUPL (a much better find-and-replace, as well as a deep undo stack). Among its many features, UltraEdit has the ability to run DOS commands from within an editing session, passing the filename of the source file into whatever program is being run. I am learning to exploit this feature to run a batch file that executes cupl.exe to compile the source, following by fit<device>.exe to generate the JEDEC fuse map. This reproduces most of the convenience of the WinCUPL IDE, sans the brain-deadedness.
The one unavoidable annoyance with WinCUPL is what appears to be a memory leak in the WinSim simulator. One can run only so many simulations and then WinSim reports errors until the program is terminated and restarted. I find this particularly nasty, as within WinSim I have the display configured in a certain way to accommodate my lame vision. Unfortunately, most of those display settings can’t be saved so they will automatically load at startup.
Welcome. Have you posted anything about your project? What are you building in which you have to solder a bunch of wires to a PLCC socket?
So I rationalize my continued use of WinCUPL by telling myself that, yes, that environment can be un dolor real de huevos, as one might say in Spanish (PM me if you need the translation
), but less so than dealing with integrating two completely unrelated programs to produce something that may be used to program an Atmel CPLD. CUPL the language can be syntactically obstreperous, although I suppose the same could be said about other hardware development languages. I’ve learned the CUPL booby traps and mostly don’t have trouble with them. I’m still trying to understand the state machine stuff—it’s not explained well in the CUPL manual, something that I would eventually like to master.In dealing with WinCUPL and its annoyances, treating the compiler and fitter as standalone programs seems better than running them from within the editor. Standalone operation is somewhat clumsy, although use of DOS batch files helps in that regard. Standalone execution has the distinct advantage of making error output from the compiler and fitter visible—normally such output is buried by the GUI. I have found the fitter’s unexpurgated error output to be useful in resolving obscure fit problems.
I have been doing my source editing in UltraEdit, which is a far better editor that that integrated into WinCUPL (a much better find-and-replace, as well as a deep undo stack). Among its many features, UltraEdit has the ability to run DOS commands from within an editing session, passing the filename of the source file into whatever program is being run. I am learning to exploit this feature to run a batch file that executes cupl.exe to compile the source, following by fit<device>.exe to generate the JEDEC fuse map. This reproduces most of the convenience of the WinCUPL IDE, sans the brain-deadedness.
The one unavoidable annoyance with WinCUPL is what appears to be a memory leak in the WinSim simulator. One can run only so many simulations and then WinSim reports errors until the program is terminated and restarted. I find this particularly nasty, as within WinSim I have the display configured in a certain way to accommodate my lame vision. Unfortunately, most of those display settings can’t be saved so they will automatically load at startup.
martingi wrote:
Still not done soldering all the wires onto that PLCC socket. But will let you know how it went!
Welcome. Have you posted anything about your project? What are you building in which you have to solder a bunch of wires to a PLCC socket?
Last edited by BigDumbDinosaur on Tue Apr 22, 2025 2:23 pm, edited 1 time in total.
x86? We ain't got no x86. We don't NEED no stinking x86!
Re: ATF15xx Verilog/VHDL using Quartus 13.0 SP1
I, too, am following this discussion with interests. I have the same frustrations with WinCUPL and pof2jed: WinCUPL is horribly inefficient especially with state machine and buried logic even if the buggy user interface is worked around; pof2jed is a disappointment that works well enough with simple designs, but then introduces random bugs when designs become complex. However, my own 25-year positive experiences with buggy and obsolete PC board layout tools (WinDraft and WinBoard by Ivex) showed that with sufficient efforts and experiences, one can overcome these buggy problems, so I'm following the discussion closely.
In the meantime, I've bought whole bunch of EPM7xxx CPLD so I can design everything in Quartus.
Bill
In the meantime, I've bought whole bunch of EPM7xxx CPLD so I can design everything in Quartus.
Bill
Re: ATF15xx Verilog/VHDL using Quartus 13.0 SP1
The promised report: there is life in my ATF1502S chips.
The "all those wires" project: just a breakout board with a PLCC socket and decoupling caps to test things. Still haven’t soldered all the wires, but enough for JTAG and power and clock and some outputs.
First experiment was to output the clock, as well as /2, /3 and /4 to four output pins. I did that in WinCUPL in a Windows VM, created a .svf file using ATMISP, and flashed that onto the chip using openocd on macOS. A mess of flying wires working up to 60MHz or so. Happy camper, despite the dolor de huevos.
So on to Quartus. I did the same thing in Verilog, and compiled it. I then used POF2JED from the command line (with the correct 7xxxS and 1502AS parts everywhere). Then ATMISP again to get a new .svf file. Also flashed that using openocd, and dontcha know, that also worked! With a lot less dolor too.
What this is for, well… dare I mention it here… they’ll be going into a Z80 based machine, basically because I grew up with a Speccy when everybody else had a C64. One CPLD for switching UART baud rates by software (you see why I’m interested in clock/3) and another for a bank switching MMU.
Martin
P.S: I missed your answers because I didn’t get back to this page. Is it possible to get mail notifications when someone posts into a thread?
The "all those wires" project: just a breakout board with a PLCC socket and decoupling caps to test things. Still haven’t soldered all the wires, but enough for JTAG and power and clock and some outputs.
First experiment was to output the clock, as well as /2, /3 and /4 to four output pins. I did that in WinCUPL in a Windows VM, created a .svf file using ATMISP, and flashed that onto the chip using openocd on macOS. A mess of flying wires working up to 60MHz or so. Happy camper, despite the dolor de huevos.
So on to Quartus. I did the same thing in Verilog, and compiled it. I then used POF2JED from the command line (with the correct 7xxxS and 1502AS parts everywhere). Then ATMISP again to get a new .svf file. Also flashed that using openocd, and dontcha know, that also worked! With a lot less dolor too.
What this is for, well… dare I mention it here… they’ll be going into a Z80 based machine, basically because I grew up with a Speccy when everybody else had a C64. One CPLD for switching UART baud rates by software (you see why I’m interested in clock/3) and another for a bank switching MMU.
Martin
P.S: I missed your answers because I didn’t get back to this page. Is it possible to get mail notifications when someone posts into a thread?