Well, first... I'll applaud your desire to design and build something. Second, I'll endorse your self quote (Frankly, I have no idea what I'm doing).
In addition to what Enso said:
1- The section for Tie High or Not. This makes no sense. Also adding an LED is of no value... either interrupt (IRQ/NMI) happens so quickly you'll never see a flash. Just use 3.3K resistors (all separate) and tie the signals to Vcc.
2- Reset Circuit. In short, it's not a proper reset circuit and switch bounce will make it highly sporadic. Just get a DS1813 and use it.
3- Power Indicator circuit. Look at what you're doing.... a 22 ohm resistor driving the LED. That will result in about 150ma of current into the LED! It's either a beacon, very hot or burned out. It will also be pushing half a watt into the 22-ohm resistor. I use small LEDs that can run off of 1ma of current, so I use a 3.3K dropping resistor.
4- Clock circuit. Looks like you're using a clock oscillator with a enable pin... what's the purpose of doing this? If you want to stop the clock, perhaps look at circuitry that can reliably stop the clock in either a high or low state, i.e., not an open/floating pin.
5- Memory Decode circuit. You should probably show this as the individual gates, much easier for anyone to look at the actual gate function. Also, seems many newbies are trying to do some bare minimum variation on Garth's original circuit. It's a very simple design on purpose... but I think you need to figure out what the goal of your first design is supposed to do... and what you intend to do with it.
6- Processor. You seem fixated on using a soft-core on a FPGA, which is fine. However, never having built a 6502 system, perhaps using a real W65C02 first would be beneficial. Once you have a working design, you can start swapping out the real 6502 for the FPGA soft-core CPU.
I would strongly suggest looking at some designs that other have built over the years. That will give you more insight on what you might want to do. Writing down the design goals can be useful.
Another minimal design I always liked was Doug Beattie's. Granted, it used 2 chips for logic decode, but had a full 32KB of addressable RAM and additional I/O selects.
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