So I've got a project that used a variant of the 6800 that was developed for automotive applications (pinout similar to the 6800, but had the 6801 instruction set).

The CPU I was using was a used part and apparently is dead in the water... I did manage to find one remaining source but they want over $50 apiece.

So, I'm looking at various approaches, and one is re-coding to run on the 65816.

Is there any kind of reference how to implement various 6800-class instructions on the 65xx CPUs? I am MUCH more familiar with the 65xx CPUs anyway as I once had a C64.

The instructions I'm interested in at the moment are TST, BGT, BLE, BLT.

Since TST checks for the Z and N flags, would a CMP #$00 do the same thing?

Hi, Meterman!

Translating 68xx to 65xx is a nice way to spend lots of your time. I did so for the VTL-2 interpreter, and found that the missing B accumulator and the narrow X and S registers required some careful treatment. This was solved by bringing the 65xx's excellent indirect addressing modes into play, but definitely took considerable thought and effort to do it efficiently. A simple example would be to keep the 68xx X register in the 65xx zp and use (zp,X) with x = 0 or (zp),Y with Y = offset, but that's definitely over-simplifying. If you go with the 65c816, you can ease some of the translation burden by going to native mode and selecting 16-bit index registers (and applying XBA as appropriate).

The best way to implement the test instruction depends somewhat on what you're testing. For TSTA you can use ORA #0. For TST memory you can substitute LDY memory. CMP #0 will TSTA, but will also set the carry flag.

BGT, BLE and BLT can all be synthesized with two (or worst case three?) 65xx branch instructions. It's important to remember that the 65xx uses the idea that a borrow from a subtract or a compare clears the carry flag, which can twist you up from time-to-time. That, and the 65xx is little-endian.

Code density should slightly favor the 68xx for typical activities, and cycle counts should slightly favor the 65xx ... if you're doing it right

Good luck, and let us know how things go.

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Got a kilobyte lying fallow in your 65xx's memory map? Sprinkle some VTL02C on it and see how it grows on you!

Mike B. (about me) (learning how to github)

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Welcome, Meterman!

Once you have a bit of a grounding in the instruction sets, a good old-fashioned single page reference card might be a good way to compare and constrast.

It took me a while to find them, for some reason, but here are the one page programmers guides from Jonathan Bowen of the Oxford University Computing Laboratory, and specifically

6502 MICROPROCESSOR Instruction Set Summary
6800 MICROPROCESSOR Instruction Set Summary

(Previous thread: Instant Reference Card)

If you are testing a memory location, take a close look at the 6502 BIT instruction. Like the 6800 BIT, it ANDs register A with the memory location to determine the Z flag. But it also determines the N and V flags based solely on the upper two bits of the memory location (unaffected by the contents of register A) making for a very efficient way to implement a couple of flags within a memory location. I wish the 680x had something similar.

You can somewhat make up for the loss of accumulator B by moving values into registers X or Y. There are a few times when the two not-quite-accumulators X and Y are better than the second full-accumulator B.

BGT, BLE and BLT are for signed comparisons. You cannot use CMP for the test because it does not affect the V flag. You must use the combination of SEC followed by SBC.

Speaking of, the 6502 does not have add without carry or subtract without borrow; be careful to do CLC before ADC and SEC before SBC if you do not want a carry or borrow involved.

If your assembler provides BLO as an alias for BCC and BHS for BCS, use them where appropriate to make your code more obvious. For example,

instead of

If your assembler does not, create a macro to do that if your assembler supports them.

Finally, it is easy to be spoiled by the variety of conditional branches on the 680x. Even the 68000 comes up short.

If your 680x code does this:

do this on the 6502:

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Thanks all for the welcome and the encouragement on the challenge ahead of me.

I already know that I have a BIG task ahead of me. The other option currently on my plate is translating the 68xx into C++ instead…

As for addressing modes, fortunately the indexed mode don’t come into play that much, as most is used as a hard-coded offset (that can be substituted for the destination location directly) or is so written that rearranging the base and index into 65xx style is almost trivial.

The bulk of the code uses zero page (locations $00-$0F and $80-$E2), with some absolute addressing ($0C00-$0C3F and $0CF8-$0CFF).

The three branch instructions I mentioned I am fairly certain are the only non-65xx branches used in my code (the code also makes use of BPL / BMI, BEQ / BNE, BCC / BCS - those I’m not worried about, and it seems the 65816 adds the BRA instruction which I also have in the code).

The BIG headache, though, is going to be math - the 16-bit D register actually sees a fair bit of usage. ...there is even a a single subroutine that contains the MUL operand.

I can provide a breakdown of the specific opcodes and modes used, OR if it's okay with you all, I can attach a text dump of the interrupt routine (If I can master this routine, the rest should fall in fairly easily) so you can see how the code is.

Also, if it helps, I can lay out the memory map that the code uses (it’s kinda weird because partial address decoding).

I will definitely look for the book suggested later today.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Here's the interrupt code I mentioned.