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Jmstein7
 Post subject: VHDL 6551 ACIA? Seen it?
PostPosted: Sun May 30, 2021 4:23 pm 
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Hi, all. Question: has anyone seen this core before? https://github.com/LIV2/VHDL-6551-ACIA

I found it on github, but I can't seem to find anything about it or its author.

Just curious.

Jonathan
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BigEd
PostPosted: Sun May 30, 2021 5:28 pm 
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(LIV2 is a member here, if not a frequent poster:
viewtopic.php?p=63845#p63845
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Jmstein7
PostPosted: Sun May 30, 2021 5:52 pm 
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BigEd wrote:
(LIV2 is a member here, if not a frequent poster:
viewtopic.php?p=63845#p63845
)


Thanks again. Hopefully, I can contribute something useful here in the not-so-far future.
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LIV2
PostPosted: Sun May 30, 2021 8:09 pm 
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Hey! It's one of my first HDL projects and I'm cringing after looking at it... Pretty much does what it says on the tin - hardly tested beyond me playing around with a fpga clone of my SBC of the time.
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Jmstein7
PostPosted: Mon May 31, 2021 2:32 pm 
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Yet, at the same time, it is pretty much the only soft 6551 out there. And, as you said in the readme, it doesn't have the bug present in the physical '51. Pretty impressive!
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GARTHWILSON
PostPosted: Mon May 31, 2021 6:43 pm 
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Jmstein7 wrote:
Yet, at the same time, it is pretty much the only soft 6551 out there. And, as you said in the readme, it doesn't have the bug present in the physical '51. Pretty impressive!

Bill Mensch (president of WDC) said that their W65C51 design simulated correctly in the industrial chip-design software they were using, but that there was a race condition the simulation software didn't catch.

Regarding a different bug, the following is from my 6502-oriented RS-232 primer, nearly halfway down the page:

      A note should be made here regarding CTS and the 6551. An applications note I have here for the Synertek NMOS 6551, as well as the '87 Rockwell data book's NMOS 6551 pages say that transmission of an already-started frame will stop immediately when CTS is taken false, the byte will be lost, and the TD line will go to marking. I consider this to be either a serious bug, or an idiotic part of the original NMOS design. The same Rockwell book says that the CMOS 65c51 will finish the already-started byte before halting transmission after CTS goes false. (IOW, they corrected that problem when they did the CMOS design.) The other data sheets I have only say CTS must be true for the ACIA to transmit, without giving details of what happens when CTS is taken false in the middle of a frame. My expectation then is that regardless of brand, the CMOS ones generally will finish the frame whereas the NMOS ones won't. If it matters in your use, you will want to experiment with the particular brand of 6551 you have in order to make sure your program operates it correctly so as not to lose data. If the NMOS 6551 is interrupted during a frame transmission, the program will have to give it the same byte again to transmit when CTS goes true. I have used a couple of different brands of 65c51 (ie, CMOS) for decades and never had that trouble with it. In fact, everything I've ever done with the 65c51 worked on first try, except when I lacked a capacitor in the crystal circuit. (If you're using just a crystal and not a separate oscillator, the crystal goes from pin 6 to pin 7 of the DIP, but you need a 22pF capacitor from pin 6 to ground.) The only thing I don't like about the 65c51 is that a couple of the controls are merged into the same control bit, where it would be nice to be able to control them separately instead. (Caveat: I have not used WDC's 65c51 which has a different transmit bug mentioned six paragraphs up.)

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Jmstein7
PostPosted: Mon May 31, 2021 7:12 pm 
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It would be great if more people worked on soft 65xx peripheral cores, like the VIA as well as the ACIA. There really is not a lot out there, yet there are a ton of 6502 and ‘c02 cores and projects. There are even some chips that could be resurrected, such as the CIA (which I hear was popular). Perhaps even some soft MMUs? If I could, I would. Oh, well - one day.
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BigDumbDinosaur
PostPosted: Mon May 31, 2021 8:02 pm 
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Jmstein7 wrote:
It would be great if more people worked on soft 65xx peripheral cores, like the VIA as well as the ACIA. There really is not a lot out there, yet there are a ton of 6502 and ‘c02 cores and projects. There are even some chips that could be resurrected, such as the CIA (which I hear was popular). Perhaps even some soft MMUs? If I could, I would. Oh, well - one day.

The tricky part about soft-coring 65xx peripherals is faithfully reproducing the bugs many of them seem to have. :D In particular, the CIA has two: the timer-B IRQ bug and the TOD alarm clock bug. Then there is the shift register bug of the 65C22, the stuck TxD ready bit in the 65C51...

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Jmstein7
PostPosted: Mon May 31, 2021 10:25 pm 
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BigDumbDinosaur wrote:
Jmstein7 wrote:
It would be great if more people worked on soft 65xx peripheral cores, like the VIA as well as the ACIA. There really is not a lot out there, yet there are a ton of 6502 and ‘c02 cores and projects. There are even some chips that could be resurrected, such as the CIA (which I hear was popular). Perhaps even some soft MMUs? If I could, I would. Oh, well - one day.

The tricky part about soft-coring 65xx peripherals is faithfully reproducing the bugs many of them seem to have. :D In particular, the CIA has two: the timer-B IRQ bug and the TOD alarm clock bug. Then there is the shift register bug of the 65C22, the stuck TxD ready bit in the 65C51...


It gives them character and charm? :lol:
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floobydust
PostPosted: Tue Jun 01, 2021 12:11 am 
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Jmstein7 wrote:
BigDumbDinosaur wrote:
Jmstein7 wrote:
It would be great if more people worked on soft 65xx peripheral cores, like the VIA as well as the ACIA. There really is not a lot out there, yet there are a ton of 6502 and ‘c02 cores and projects. There are even some chips that could be resurrected, such as the CIA (which I hear was popular). Perhaps even some soft MMUs? If I could, I would. Oh, well - one day.

The tricky part about soft-coring 65xx peripherals is faithfully reproducing the bugs many of them seem to have. :D In particular, the CIA has two: the timer-B IRQ bug and the TOD alarm clock bug. Then there is the shift register bug of the 65C22, the stuck TxD ready bit in the 65C51...


It gives them character and charm? :lol:


Hmmm, being the one who found the bug in the latest W65C51 (xmit bit stuck on), I can assure you there's no fun or charm. It was many hours of debugging with a scope and logic analyzer and buying 13+ chips from different vendors. All of that just to find out that they're defective and completely useless with EVERY piece of software written for a (working) 65(C)51. If you find it charming... well, there's a bug/defect for everyone I guess.

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BigDumbDinosaur
PostPosted: Tue Jun 01, 2021 1:01 am 
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floobydust wrote:
Jmstein7 wrote:
BigDumbDinosaur wrote:
Jmstein7 wrote:
It would be great if more people worked on soft 65xx peripheral cores, like the VIA as well as the ACIA. There really is not a lot out there, yet there are a ton of 6502 and ‘c02 cores and projects. There are even some chips that could be resurrected, such as the CIA (which I hear was popular). Perhaps even some soft MMUs? If I could, I would. Oh, well - one day.

The tricky part about soft-coring 65xx peripherals is faithfully reproducing the bugs many of them seem to have. :D In particular, the CIA has two: the timer-B IRQ bug and the TOD alarm clock bug. Then there is the shift register bug of the 65C22, the stuck TxD ready bit in the 65C51...

It gives them character and charm? :lol:

Hmmm, being the one who found the bug in the latest W65C51 (xmit bit stuck on), I can assure you there's no fun or charm. It was many hours of debugging with a scope and logic analyzer and buying 13+ chips from different vendors. All of that just to find out that they're defective and completely useless with EVERY piece of software written for a (working) 65(C)51. If you find it charming... well, there's a bug/defect for everyone I guess.

...which is why I started the topic about using the NXP UARTs.

Speaking of bugs, we don't want to leave the 65C02 out in the cold, eh? Let's not forget the bug discovered when an indexed access is done with the base address lying on a page boundary. That does wonders for trying to set up MR0 in a 28L92. :D

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floobydust
PostPosted: Tue Jun 01, 2021 2:01 am 
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BigDumbDinosaur wrote:
floobydust wrote:
Jmstein7 wrote:
BigDumbDinosaur wrote:
Jmstein7 wrote:
It would be great if more people worked on soft 65xx peripheral cores, like the VIA as well as the ACIA. There really is not a lot out there, yet there are a ton of 6502 and ‘c02 cores and projects. There are even some chips that could be resurrected, such as the CIA (which I hear was popular). Perhaps even some soft MMUs? If I could, I would. Oh, well - one day.

The tricky part about soft-coring 65xx peripherals is faithfully reproducing the bugs many of them seem to have. :D In particular, the CIA has two: the timer-B IRQ bug and the TOD alarm clock bug. Then there is the shift register bug of the 65C22, the stuck TxD ready bit in the 65C51...

It gives them character and charm? :lol:

Hmmm, being the one who found the bug in the latest W65C51 (xmit bit stuck on), I can assure you there's no fun or charm. It was many hours of debugging with a scope and logic analyzer and buying 13+ chips from different vendors. All of that just to find out that they're defective and completely useless with EVERY piece of software written for a (working) 65(C)51. If you find it charming... well, there's a bug/defect for everyone I guess.

...which is why I started the topic about using the NXP UARTs.

Speaking of bugs, we don't want to leave the 65C02 out in the cold, eh? Let's not forget the bug discovered when an indexed access is done with the base address lying on a page boundary. That does wonders for trying to set up MR0 in a 28L92. :D


Yup.. lived through that one when I wrote the BIOS for the NXP/Philips SCC2691 UART. At least the end result was worth the experience 8)

Then again... the posts on that dev cycle included the usual "culprits"... Jeff, Garth and you... IIRC.

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Jmstein7
PostPosted: Tue Jun 01, 2021 4:45 pm 
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Ah. Feels good to finally be a part of the conversation. -Jon
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Rob Finch
PostPosted: Sun Jun 13, 2021 4:13 am 
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Just thought I'd mention my 6551 uart core. It is verilog code, but many toolsets will accept either verilog or VHDL.
While it is 32-bit it can function as 8-bit by using only the low order eight bits of the data bus.

https://opencores.org/projects/uart6551

Geared towards 6551 compatibility in a 32-bit environment.

I have code for a VIA too, but I have not posted it.

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Jmstein7
PostPosted: Sun Jun 13, 2021 1:34 pm 
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Rob Finch wrote:
Just thought I'd mention my 6551 uart core. It is verilog code, but many toolsets will accept either verilog or VHDL.
While it is 32-bit it can function as 8-bit by using only the low order eight bits of the data bus.

https://opencores.org/projects/uart6551

Geared towards 6551 compatibility in a 32-bit environment.

I have code for a VIA too, but I have not posted it.

That's really cool. I'm going to try it out. And, I prefer verilog, too. Post the 6522 as well!

-Jon
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