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PostPosted: Wed May 12, 2021 12:02 pm 
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sark02 wrote:
Some good ideas here. What would be interesting, I think, would be to extend the memory map over a high speed serial link (think: SPI clocked at 200MHz, providing an effective memory bandwidth of around 16MB/s). The idea could be that you capture the PHI2 cycle when the address is being output, then stop the clock while the SPI engine serializes the transaction to external memory.


Are you talking about serializing memory? Serial RAM?


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PostPosted: Wed May 12, 2021 12:04 pm 
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tokafondo wrote:
Or even better: have dedicated 6502 chips for intensive I/O tasks that would run by themselves in separated hardware spaces, but that could be inspected by the main '816 when required.


I've realized that this is basically what a modern computer, as it's usually understood, is: an ecosystem of microcontrollers.


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PostPosted: Wed May 12, 2021 12:07 pm 
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BigEd wrote:
Also Bob's diagram is rather good, but it's a reference, not a practical exercise. I think practical exercise is crucial.
viewtopic.php?p=42766#p42766


Thanks for this. Very visual and useful.


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PostPosted: Wed May 12, 2021 12:11 pm 
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I see there's a link in that thread to this one, which has lots of resources:
Best way to start learning 6502 Assembler


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PostPosted: Fri May 21, 2021 11:26 am 
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I love these newbie questions; in part because I used to have similar ideas. When they differ from my newbie questions, I learn more about the mindset of a layperson interested in technology and I hope it makes me a better communicator.

Is it possible to have virtual instances of a 6502 system? Yes. The hardware is relatively simple. The software is as difficult as you want it to be and it may be the most difficult software which you ever write.

Not a 6502 example, but I've seen a multiplexed clone of a Sinclair ZX Spectrum. The original models were shipped with 16KB DRAM or 48KB DRAM. A friend of a friend wanted to clone the 48KB DRAM model for reasons which were never explained to me. However, at the time of construction, the smallest DRAM chips were one megabit and the recently introduced four megabit chips were obscenely expensive. Unless you are in the habit of making particularly perverse multiplexing circuits, eight separate one megabit chips are most conveniently arranged into 1MB DRAM. But who would want to implement a Sinclair ZX Spectrum and only use 3/64 of the DRAM? Therefore, it differed from the original by providing 16 virtual instances of a Sinclair ZX Spectrum where only one was running at any time.

I have no idea how this was implemented. Presumably, instance switching occurred at a common point of the screen refresh cycle. However, that doesn't explain how each instance would be initialized using an illegal copy of the unmodified Spectrum ROM.

The most obvious limitation of this implementation was the absolute lack of communication channels between the virtual instances. It would be brilliant if it were possible to increment and decrement through virtual instances and use it like a big undo when programming. But, no. It had no such functionality. It was also possible to do stupid things that were guaranteed to fail, such as switch instance while loading from tape. Also, don't expect peripherals, like printer or disk to work when you switch. Likewise, there are no background tasks.

When people say it is difficult, this is the type of difficulty they anticipate.

Is it possible to have virtual instances of a 6502 system? Yes.

It is possible to have virtual instances which communicate among themselves so they can run tasks in the background, not foobar the filing system, share a printer, network connection, audio and video? Yes but it is hideously difficult.

Writing an application is difficult. Writing a system resource, such as a database, is more difficult. Writing a device driver or filing system is another level of difficulty. Writing an operating system to co-ordinate resources is the most difficult of all. Part of the difficulty is the lack of diagnostics and debug. When an application fails, it typically fails on a relatively stable system. But how do you debug an operating system before you integrate the filing system? Likewise, it is difficult to simultaneously debug hardware and software. Is it one? Is it the other? It is both? It is me?

Anyhow, keep learning about hardware and software but I strongly recommend working down the software stack (from application to operating system) as you become proficient at each tier.

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PostPosted: Thu May 27, 2021 12:38 pm 
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sark02 on Wed 12 May 2021 wrote:
capture the PHI2 cycle when the address is being output, then stop the clock while the SPI engine serializes the transaction to external memory.


You may be interested in a memory mapped quad SPI interface which is primarily intended for networking and MicroSD storage. The example circuit diagram only serializes 8 bits of address. This could easily be extended to cover arbitrary ranges of memory. Furthermore, it is entirely feasible for each interface to be significantly faster than a Transputer link.

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