I try to create some kind of W65C02S based computer, and until now, it worked pretty well, but I ran into some snags now. I have no idea how to continue, so I'll just tell what I tried and perhaps somebody can give me some hints or tips.

The design is just the 6502, with 32kB RAM and 32 kB ROM, using A15 to select RAM or ROM. There is some glue logic currently (both 74HC and 74LS chips) for future I/I expansion on addresses 7ff8 to 7fff (the glue logic disables both RAM and ROM in that address range).

What I am experiencing now is that whenever there is a WRITE (e.g. to RAM), the databus completely fails, as if the 6502 cannot drive it. When measuring, I can see a noisy 1,8V instead of a clear 0 or 5. READs go fine. I have connected an Arduino to monitor the address and databus (and some control signals) and I can see the correct stuff passing by when single stepping.

I have no clue how to continue now, but some research gives me a few leads:

1. I somehow destroyed the 6502 and it is unable to drive the databus.
2. I am using incorrect glue logic, mixing LS and HC chips, even though the datasheets tell me they should all work on 5V.
3. Some wiring issue (obviously I looked, but haven't found anything yet)
4. Anything else?

Speed is not an issue as I am still single stepping the whole thing.

1.8V level pretty much means you have a data contention. Please upload your schematic. Very unlikely you've damaged any parts.
Bill

When I measure now with a multimeter, I get 0.3-0.7V, not 1.8.

I did see the 1.8 earlier on an osscilloscope.

Attached my design.

It's pretty complicated... Did you get a chance to look at Garth's 6502 primer?

I don't think that you qualify the memory write with PHI2... Or I didn't see it.

Seriously, consider replacing all your decoding logic with a single 74hc00. When you truly miss the 'wasted' 16K, you will probably be able to decode in a less convoluted way. It is rarely a good idea to make your life difficult today to prepare for 'the future' as you see it now.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Thanks, I haven't read the primer. Seems like a lot of information there. I'll have to study that.

I'll go a step back and make my design simpler.

Definitely need to qualify chip selects with PHI2 high. I/O decoding is too complicated and slow, simplification is good for the first try.
Bill

What exactly do you mean with "qualify chip selects with PHI2 high"?

I am not a native speaker and haven't heard the term "qualify" in this context before.

Chip select should not be asserted (going low) until Phi2 is high. This is because addresses may be changing while Phi2 is low. Addresses and controls are not guaranteed to be valid until Phi2 is high.
Bill

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

As BDD noted, this advice does not apply to 65xx peripheral chips (their chips selects must not be qualified with Phi2 high).

But your design has no 65xx peripheral chips, so the only sources of concern are the RAM and to the two '273 output ports. These all need to be protected from spurious writes during the Phi2-low period (during which addresses are in transition and can't be trusted).

For the RAM you need to ensure that either (or both) /CE and /WE are high during the Phi2-low period, as Garth said.

As for the two '273 output ports, only one is presently protected. I see Phi2 is included in the logic which drives one 273's clock input, but not the other.

Attached is simple solution that protects both. Variations are possible, but the main thing is that I've replaced your '137 with a '138, and Phi2 directly drives the 138's active-high Enable input, thus preventing spurious writes.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html