Skinny 64K SRAM Chip, W24512AK-10 $0.50 (including shipping)

[Michael]

A potential 'bargain' for a single skinny 64K W24512AK-10, 15, or 20 SRAM chip at $0.50, $0.52, or $0.55, respectively, including shipping. I've not dealt with this vendor before.

Other skinny SRAM chips I've purchased before include IS61C512-15N (64K) or IS61C1024-15N (128K) at 60 cents each for quantity 5 and UM61512AK-15 (64K) quantity 5 (free).

Purchasing chips from Aliexpress vendors is somewhat "hit-or-miss" but Aliexpress has been very good at providing refunds on disputes.

Cheerful regards, Mike, K8LH

[cjs]

I found a data sheet for this part, and it does seem that the -10, -15 and -20 suffixes are indeed the read cycle time in nS. So it seems odd that the parts get more expensive as they get slower. (My current prices more or less match the ones in your image: ¥56, ¥58 and ¥61 each.) Any idea what's up with that?

And did you get yours, Mike? How did they work out for you?

[Michael]

I received them last week. I had ordered one of each speed but received all -15 parts. They're "pulls" but in very nice condition. All three tested ok...

[BigEd]

cjs wrote:

I found a data sheet for this part, and it does seem that the -10, -15 and -20 suffixes are indeed the read cycle time in nS. So it seems odd that the parts get more expensive as they get slower. (My current prices more or less match the ones in your image: ¥56, ¥58 and ¥61 each.) Any idea what's up with that?

All I can think of is that the slower ones are more popular, perhaps because they use a little less power (according to the datasheet.)

[Chromatix]

Does the datasheet specify the power consumption at rated minimum cycle time? If so, it would be natural for the power consumption to go up when running faster. It's more useful for a datasheet to list static and dynamic power draw separately, with the dynamic power draw normalised to a standard cycle rate.

[cjs]

Well, they're cheap enough that I ordered a few. I ordered only one from the original listing becuase the free shipping to Japan increased to ¥117 for two and ¥525 for 3+, which kinda destroyed the pricing on it, but then I discovered another listing (slightly cheaper per part, ¥49-¥50, depending on speed, and this time the slower parts are cheaper) that charges a flat ¥47 to ship to Japan for qty. 1-5. (I suppose I could do just as well by submitting five separate single chip orders to the first vendor, but that's not worth the hassle.)

Normally the unusual size would be an annoyance for me, and not worth saving fifty cents or a buck on parts for a project, but the smaller parts offer advantages in certain applications with limited PCB or protoboard space, such as C64 cartridges.

I wonder, did JDEC ever standardize the narrower packaging, or did some vendors just decide to use it?

[BillO]

Chromatix wrote:

Does the datasheet specify the power consumption at rated minimum cycle time? If so, it would be natural for the power consumption to go up when running faster. It's more useful for a datasheet to list static and dynamic power draw separately, with the dynamic power draw normalised to a standard cycle rate.

Yes it does. You would think these are power hogs from the datasheet. They say they consume about 200ma (for the 15ns parts at full tilt) while active with zero I/O current. However, in 'real life' operation the average consumption is more like 30ma based on the ones I use in my designs @ 14MHz. They are the most power hungry chips in those designs with the whole board consuming about 85ma. Not really suitable for battery applications unless you don't mind having to change/charge batteries often, but certainly not the result you would expect from the datasheet. But then again, at 14MHz they are just loping along. Quiescent current draw is about 10mA.

[enso]

I've become a big fan of these.

Due to their unusual shape, they are less likely to be fakes. I was suspicious of the speed grade, but I doubt it is worth it to sand and etch for that reason alone, just to sell the result for fifty cents.

According to the spec (see post above), output-enable to output-valid time is roughly 1/2 of the nominal rating, 7ns for a 15ns part. Chip-select-access time is 15ns... Keeping the chip enabled may be a little faster. Although the write cycle is longer, so I am not sure it matters. 15ns is pretty fast.

I posted a gEDA-pcb footprint viewtopic.php?f=4&t=6598.

[plasmo]

The pin assignments are close enough to a EPROM to place under the EPROM resulting in a smaller board, and short fast connections. At 50 cents, just solder the part directly to the pc board; EPROM is always socketed anyway so that takes no additional vertical space.
Bill

[BillO]

plasmo wrote:

The pin assignments are close enough to a EPROM to place under the EPROM resulting in a smaller board, and short fast connections. At 50 cents, just solder the part directly to the pc board; EPROM is always socketed anyway so that takes no additional vertical space.
Bill

What a cool idea! Have to investigate this...

[jds]

plasmo wrote:

The pin assignments are close enough to a EPROM to place under the EPROM resulting in a smaller board, and short fast connections. At 50 cents, just solder the part directly to the pc board; EPROM is always socketed anyway so that takes no additional vertical space.
Bill

I'm pretty sure a lot of Rockwell modem ISA cards used to do this. They have a 6502 based MCU, some of them get up to quite high clock speeds too, but they have a register that enables slowing down the bus if needed. Looking at pictures of these boards there are some with RAM chips and some that look like they have none, but they have a socketed ROM or EPROM and the RAM sits underneath. I'm not sure what the benefit is to them, but I guess they are trying to keep the PCB size as small as possible.

[zeefour]

jds wrote:

plasmo wrote:

The pin assignments are close enough to a EPROM to place under the EPROM resulting in a smaller board, and short fast connections. At 50 cents, just solder the part directly to the pc board; EPROM is always socketed anyway so that takes no additional vertical space.
Bill

I'm pretty sure a lot of Rockwell modem ISA cards used to do this. They have a 6502 based MCU, some of them get up to quite high clock speeds too, but they have a register that enables slowing down the bus if needed. Looking at pictures of these boards there are some with RAM chips and some that look like they have none, but they have a socketed ROM or EPROM and the RAM sits underneath. I'm not sure what the benefit is to them, but I guess they are trying to keep the PCB size as small as possible.

The VCF 6502 Badge (Lee Hart et al.) uses the same trick. The RAM sits under the ROM. You have to cut the socket down to just the sides to accommodate the RAM chip, and solder the RAM directly to the board, but it works great (at least for mine). Different RAM chip in the Badge I think, but same idea. With the "deluxe" parts you get 32K ROM over 32K RAM. Makes sense for something like the Badge so that you can fit all the components into a small space.

[GARTHWILSON]

About the stacking, a great topic with lots of pictures is viewtopic.php?f=4&t=4142 . (Be sure to see the 2nd page, too.)

[enso]

There are great space-saving and electrical reasons for tucking the SRAM into the socket of the EPROM.

As demonstrated, it is also possible to tuck the SRAM under the CPU, on a DIP40-sized board. I am experimenting with one such design. The SRAM is a little shorter, leaving space for decoupling, a SOT23 reset supervisor and an SMD pullup resistor pack. A minimal system just needs a clock, a ROM and a 74HC00. There is actually enough room for a SOIC-14 '00, but I did not want to hardwire the system to that extent. Instead I expose the /CS and /OE of the SRAM, which allows the assembly to be used in just about any map or situation.

I just need to find the best IC-like pins. In the meantime I can use my 3D-printed wire-wrap sockets.

temp.png (11.32 KiB) Viewed 4174 times

P.S. Garth, connecting the address and data pins to their exact counterparts was just an added brain teaser.

[Michael]

I designed a little 0.8-mm thickness PCB that is soldered onto the shoulder portion of the pins on the bottom of a 40-pin machined pin CPU socket to which a 64K RAM chip is installed (underneath the 65x02 CPU). Pin 35 which is 'unused' on the 40-pin 65x02 CPU is used to access the active lo RAM chip select and the active hi RAM chip select is connected to the PHI2 input to qualify RAM read/write operations. Just add a 20-pin PIC "ROM Emulator" and a VIA and/or an ACIA for a complete mini' system.

Cheerful regards, Mike, K8LH