Uh...there is no PLK instruction. In fact there is no direct programmatic means by which PB can be modified.
I think that's a typo for PLB, which is "pull data bank register from stack".
Thus, my suggestion of getting a value into A, pushing it, then popping it out into the PDR with the PLB instruction. Maybe this doesn't meet your definition of "direct". (What would?)
Chromatix wrote:
The new registers in the '816 - PBR, DBR, DPR - are active and effective even in Emulation mode. Their default values out of reset give the same behaviour as a 65C02, but if you change them, they take effect immediately, even if you haven't switched to Native mode.
Ahah! Thanks. I'm certain that I read that in emulation mode, the high 8 bits of instruction fetch addresses were forced to zero, ignoring PBR. But I can't find that now, so I must have made it up or misunderstood something.
Since A15 and A21 are swapped, in emulation mode 0x20 bank addresses will be the RAM that eventually appears in the 0x00 bank. I think, then, we can either plan the copy a little better or plan the jump a little better.
If that doesn't pan out, I think I'd rather write a "thunk" or "jump pad" to RAM from the mapped ROM. The ROM writes that code to RAM, then jumps to that code ... which enters native mode, finishes necessary initialization, and then re-enters the ROM code at the newly mapped location. This way, very few bytes need to be copied and startup can continue expediently.
Anyway, thanks for talking it through -- now that I finally understand that the program bank register is honoured in emulation mode, I've got a much better picture. I like your bank/select swapping idea, and I'm sure I'll implement something like it.
There are certainly ways of making this work! I can confirm that a long jump to a non-zero bank works in emulation mode. (But in that state you pretty much need to avoid interrupts, which only stack two bytes of PC.)
A typo for the PBR. So very sorry to not perfectly enter my thoughts. We can look up the PLB instruction, though, and see that it's target is indeed the PBR. So at least I got it half right!
A typo for the PBR. So very sorry to not perfectly enter my thoughts. We can look up the PLB instruction, though, and see that it's target is indeed the PBR. So at least I got it half right!
You don't need to get defensive about it. However, I will say accuracy in technical writing is important, especially for the benefit of those who are just learning the 6502 assembly language. With that thought in mind, please note that the PLB instruction loads DB from the stack. There is no instruction that can do the same with PB.
Anyhow, what I do in my source code comments and technical writing is to use two-letter references for registers, which among other things, prevents them from being mistakenly read as a instruction mnemonic (which "PDR" could be mistaken as). In doing so, I'm merely following something that was established by Jim Butterfield in the 1970s:
REGISTER SYMBOL COMMENT
—————————————————————————————————————————————————————————————————————————————
Accumulator .A primary 8-bit accumulator in 65C816 ('m' bit = 1)
Accumulator .B secondary 8-bit accumulator in 65C816 ('m' bit = 1)
Accumulator .C 16-bit accumulator in 65C816 ('m' bit = 0)
X-index .X
Y-index .Y
Data bank DB default data bank in 65C816
Direct page DP direct page pointer in 65C816
Program bank PB default program bank in 65C816
Program Counter PC
Stack Pointer SP
Status Register SR
—————————————————————————————————————————————————————————————————————————————
Going through old posts and ran across this one. I've built a zero glue logic Z80 SBC (with I/O), now I wonder whether it is possible to build zero glue logic 6502? Has this been talked about? If not, I can start a new thread so not to derail this one.
Bill
Edit, I think it IS possible to build zero-glue 6502 SBC with I/O
