Clock stretching using a GAL22V10

[jfoucher]

Hi,
I am currently in the planning stages of a computer
It uses a GAL22V10 on the backplane to do expansion slots address decoding.

I am wondering if it would be possible to have the clock signal (generated by an oscillator on the backplane) go though the 22V10 before reaching the expansion bus and other components to be able to slow the clock down when accessing slow devices such as the ROM. (Yes, I realize VIA timers and such would be affected, but please bear with me)
I understand I might be possible to achieve this by using registered output mode for the specific pin in the 22V10. If so great news! But I am wondering by what factor can the clock be slowed? Is it possible to have a binary counter in the 22V10 maybe?

Thanks

[8BIT]

Take a look at this -> https://sbc.rictor.org/wsgen.html

It combines some decoding with a /2 and /4 wait state generator which uses the decoded addresses to apply the proper wait.

It would be a good place to start. How much delay are you looking for?

Daryl

[jfoucher]

8BIT wrote:

It would be a good place to start. How much delay are you looking for?
Daryl

Yes, great place to start. Ideally the clock would be divided by 8. From I gather by looking at your code and the ATF22V10 datasheet though, there is only one flip flip per pin. So dividing by 8 would use three pins, is that right ? Alternatively is there a way to multiplex two clocks to one output pin depending on (to simplify) whether another pin is high or low ? This would require adding another oscillator but would only use another additional pin of the 22V10. But I'm not sure about multiplexing in WinCupl. Can you do this for example ?

Code: Select all

CLK_OUT = A15 ? CLK_SLOW : CLK_FAST

The CUPL manual I found is not really clear, and the error messages in WINCUPL were not very helpful...

[8BIT]

Yes, dividing by 8 would require 1 more output. You can easily multiplex 2 inputs. The big issue with clocks is controlling when they switch, to eliminate very short clock pulses during the transition.

Here's how a basic mux would be written:

Code: Select all

Pin 2 = A
Pin 3 = B
Pin 4 = Control
Pin 23 = Out

Out = (A & !Control) # (B & Control);

Out follows A when control is low and B when control is high.

To ensure the transition is clean, you'd have to qualify the Control signal to change only when both A&B are at the same state. That would require at least one flip-flop. You'd have to study that more to be sure it works with your application.

Daryl

[jfoucher]

8BIT wrote:

Yes, dividing by 8 would require 1 more output. You can easily multiplex 2 inputs. The big issue with clocks is controlling when they switch, to eliminate very short clock pulses during the transition.

Here's how a basic mux would be written:

Code: Select all

Pin 2 = A
Pin 3 = B
Pin 4 = Control
Pin 23 = Out

Out = (A & !Control) # (B & Control);

Out follows A when control is low and B when control is high.


To ensure the transition is clean, you'd have to qualify the Control signal to change only when both A&B are at the same state. That would require at least one flip-flop. You'd have to study that more to be sure it works with your application.

Daryl

Great, thanks Daryl I have all the info I need now. It seems both solution would use the same number of pins in my application, but the dividing by 8 with flip flops would seem to provide more flexibility with less external circuitry, so I'll probably go that route.

[jfoucher]

Daryl, sorry but I think I need your assistance once more. I have tried dividing the clock by more than two but I fail to do so because I cannot find a way to redirect the output of one flip flop to the clock of the next. I have tried the .CK extension but it seems that the device does not support it. Any advice ?
Thanks

Edit: I Finally managed to do it this way:

Code: Select all

CLK_DIV_2.d = !CLK_DIV_2; 
CLK_DIV_4.d = (CLK_DIV_2 & !CLK_DIV_4) # (!CLK_DIV_2 & CLK_DIV_4);

[jfoucher]

And here is the solution I came up with, which uses 4 output pins to select between either the full speed clock, or one that is 4 times slower:

Code: Select all

// Divide the main clock by two with a flip flop
CLK_DIV_2.d = !CLK_DIV_2; 
// Divide the /2 clock by two by using a multiplexer and another flip flop
CLK_DIV_4.d = (CLK_DIV_2 & !CLK_DIV_4) # (!CLK_DIV_2 & CLK_DIV_4);
// Check if the two possible output clocks are at the same level
TEST = CLK_DIV_4&CLK # !CLK_DIV_4&!CLK;
// If yes, the mux flip flop takes the new value, otherwise it retains the old value
MUX.d = (TEST & A15) # (!TEST & MUX);
// CLK_OUT is either CLK or CLK_DIV_4 depending on the output of Mux
CLK_OUT= (MUX & CLK_DIV_4) # (!MUX & CLK);

It's a pity that it uses so many pins, but I'm not sure if it can be optimized...

[8BIT]

I'll have a go at it, but it won't be until tomorrow.

Daryl

[jfoucher]

Oh thanks, but don't worry about it, I was just saying, not asking.