Using FM1808 as RAM

[bartleph]

Hi. I have built a 6502 dev board containing a WD65C02, 6850,27C256 EPROM,HY62256 SRAM and various decoding logic. I want to replace the SRAM with Ramtron FM1808 in order to retain programs when power is off. I have tried numerous combinations of OE/CE/WE tied low, connected to R/W etc to no avail. Does anyone have an example of a 6502 using FM1808 to help me with this problem?
Kind Regards,
Paul

[Windfall]

I used an FM1808 in 2004 for this : http://www.zeridajh.org/hardware/gommc/index.htm.

You have to take special notice of this (see the datasheet) :

Chip Enable: /CE selects the device when low. Asserting /CE low causes the
address to be latched internally. Address changes that occur after /CE goes low
will be ignored until the next falling edge occurs

This is in contrast to regular SRAM, where you can basically keep changing the address as long as there is enough time from address stable to data transfer, and you have the option to tie nCE low.

[GARTHWILSON]

bartleph wrote:

I want to replace the SRAM with Ramtron FM1808 in order to retain programs when power is off. I have tried numerous combinations of OE/CE/WE tied low, connected to R/W etc to no avail.

To successfully battery-back SRAM, try the simple circuit at viewtopic.php?p=32004#p32004 . I designed a different way in 1986 for a project at work, and it worked fine, but had a lot more components.

[Dr Jefyll]

Windfall wrote:

Chip Enable: /CE selects the device when low. Asserting /CE low causes the
address to be latched internally. Address changes that occur after /CE goes low
will be ignored until the next falling edge occurs

Thanks, John. Paul, in case this isn't clear it means /CE will need to be qualified with Phi2. Doing so will ensure that every cycle during which the FM1808 is accessed is also a cycle during which the FM1808 sees a high to low transition on /CE. Thus all address changes are guaranteed to be recognized.

Feel free to show us your glue logic if you want some suggestions on alterations to accommodate the FM1808. Alternatively, you could go back to the HY62256 and use Garth's circuit.

-- Jeff

[bartleph]

Windfall wrote:

I used an FM1808 in 2004 for this : http://www.zeridajh.org/hardware/gommc/index.htm.

You have to take special notice of this (see the datasheet) :

Chip Enable: /CE selects the device when low. Asserting /CE low causes the
address to be latched internally. Address changes that occur after /CE goes low
will be ignored until the next falling edge occurs

This is in contrast to regular SRAM, where you can basically keep changing the address as long as there is enough time from address stable to data transfer, and you have the option to tie nCE low.

Hi John. I have one of your GoSDC's for my beeb. Can I use it in place of either my 32K Eprom or 32k Sram on my dev board?

[Windfall]

bartleph wrote:

Hi John. I have one of your GoSDC's for my beeb. Can I use it in place of either my 32K Eprom or 32k Sram on my dev board?

Depends on what 'my dev board' is. Perhaps you can give more details. GoSDC is not nearly as flexible as generic ROMs or RAMs when it comes to nCE/nOE timing (because it cannot be).

[bartleph]

Dr Jefyll wrote:

Windfall wrote:

Chip Enable: /CE selects the device when low. Asserting /CE low causes the
address to be latched internally. Address changes that occur after /CE goes low
will be ignored until the next falling edge occurs

Thanks, John. Paul, in case this isn't clear it means /CE will need to be qualified with Phi2. Doing so will ensure that every cycle during which the FM1808 is accessed is also a cycle during which the FM1808 sees a high to low transition on /CE. Thus all address changes are guaranteed to be recognized.

Feel free to show us your glue logic if you want some suggestions on alterations to accommodate the FM1808. Alternatively, you could go back to the HY62256 and use Garth's circuit.

-- Jeff

Thanks Jeff,
Ok my W65C02 board has 32k ROM (27256) and 32k SRAM (62256) at present. I'm hoping to use the FM1808 instead of the SRAM.
SRAM pins:-
27(/WE) RamRW
22(/OE) RomOE
20(/CS) A15
RamRW is derived from /CPURW NANDED with Phi2
RomOE is derived from CPURW NANDED with Phi2

ROM Pins:-
20(/CE) is derived from Address decoding to allow space for ACIA
22(/OE) RomOE
All works fine with SRAM but I cannot see why FM1808 is not working.
Any help or suggestions would be very much appreciated.
TIA

Paul

[Windfall]

bartleph wrote:

SRAM pins:-
27(/WE) RamRW
22(/OE) RomOE
20(/CS) A15
RamRW is derived from /CPURW NANDED with Phi2
RomOE is derived from CPURW NANDED with Phi2

You cannot use A15 as a chip select for reasons that have been highlighted already, several times. A15 can remain 0 or 1 for many cycles and therefore does not make the required transition to act as the 'address valid' strobe that FRAM needs it to be. You need to work Phi2 into /CS, e.g. /CS = /A15 NAND Phi2.

[bartleph]

Windfall wrote:

bartleph wrote:

SRAM pins:-
27(/WE) RamRW
22(/OE) RomOE
20(/CS) A15
RamRW is derived from /CPURW NANDED with Phi2
RomOE is derived from CPURW NANDED with Phi2

You cannot use A15 as a chip select for reasons that have been highlighted already, several times. A15 can remain 0 or 1 for many cycles and therefore does not make the required transition to act as the 'address valid' strobe that FRAM needs it to be. You need to work Phi2 into /CS, e.g. /CS = /A15 NAND Phi2.

Jeff... Superb result. FRAM pin 20 is /A15 NAND Phi2 and works brilliantly!!!

Thank you.
This 6502.org forum is so valuable..

Paul

[Dr Jefyll]

You're welcome! But it was Windfall who connected most of the dots.

Intriguing devives, those Ferroelectric Nonvolatile RAMs! For anyone who's interested I'm attaching a datasheet.

-- Jeff

[Windfall]

Dr Jefyll wrote:

Intriguing devives, those Ferroelectric Nonvolatile RAMs!

Indeed. Its greatest strength (non-volatility) can be its greatest weakness (if whatever it remembers hangs the system it is in).

And reading it (as well as writing) wears out its cells. When I used it back in 2004, the 'endurance' was such that I had to run tight transfer loops outside FRAM (in normal RAM, actually on the 6502 stack) for fear of it wearing out too quickly (as in : 10 years of heavy use or so). The endurance has improved a lot since then (due to several production changes), so these days, at least if you buy recently produced chips, the wearing out should not be an issue in most if not all cases.

[GARTHWILSON]

Windfall wrote:

And reading it (as well as writing) wears out its cells.

Apparently they've solved that. The first page of the data sheet Jeff posted says, "Unlimited Read/Write Cycles."

[Windfall]

GARTHWILSON wrote:

Windfall wrote:

And reading it (as well as writing) wears out its cells.

Apparently they've solved that. The first page of the data sheet Jeff posted says, "Unlimited Read/Write Cycles."

They probably still wear out eventually, but only after hundreds of years of full speed operation.

The datasheet I have (Rev 2.3, May 2003) says 'High Endurance 10 Billion (10^10) Read/Writes'. I kept track of this for a while, back then, and I think the endurance increased by a factor of 10 or so in just one or two years (although I'm not quite sure if I have kept the earlier or later datasheet).

[cjs]

Windfall wrote:

The datasheet I have (Rev 2.3, May 2003) says 'High Endurance 10 Billion (10^10) Read/Writes'. I kept track of this for a while, back then, and I think the endurance increased by a factor of 10 or so in just one or two years (although I'm not quite sure if I have kept the earlier or later datasheet).

Am I calculating this wrong, or is 10^10 incredibly low to me for anything anybody would consider using as system RAM or ROM, especially if running code from it? At 1 MHz a 6502 will do 10^6 read/write operations per second, right? 10^10/10^6 = 10^4 = 1000 seconds, or you could run a 6502 from it for less than twenty minutes before it would wear out the FRAM. (Obviously if this were for storage of something you'd typically copy to RAM on power-up this wouldn't be such an issue; you can read an entire 8K device a million times or so.)

Which part had the 10^10 spec? I bought some FM1608s from AliExpress a while back, and according to the 2007 v3.2 datasheet (attached) they have 10^12. But even that doesn't help much: 10^6 seconds is only about 278 hours, less than a fortnight if running full-time. (You might get half a year from it if running for only an hour or two per day.) I guess before buying these I should have considered the actual number, rather than just assuming "high endurance" really would be high endurance for my application! (I intended to use these as a substitute for ROM.)

However, another three orders of magnitude on to that, 10^15, would bring it up to 31 years of continuous operation at 1 MHz, which I suppose is close enough to "unlimited" for many products (though not for all!).

I did luck out in that one of the FM1608s I bought actually turns out to be an FM18L008. These all look like pulls, so who knows how much endurance these FM1608s actually have left? Though given their relatively low endurance to start with, it seems likely that they were used in an application that did not read or write them terribly often.

Is the lifetime the same for all parts of a given part number, or might the specs have changed over the years they manufactured the part? My FM1608s appear to range from early 2004 through mid-2008, if I'm reading the date codes correctly:

Code: Select all

RAMTRON
FM1608-120-PG
M101090113G3 (×2)
M082170098G22
M074670088G18
M073270087G13
M072770087G9
M053750065G
M045340058G8
M044040057G

[GARTHWILSON]

The numbers probably had to do with individual bytes, such that even sitting in a loop waiting for a command, there would be multiple instructions in the loop, some with two or three bytes each, so it would last at least five or ten times that long in the worst case. Regardless, Jeff's data sheet says the number is unlimited now though, just like SRAM.