There's no instruction to JAM a 65c02 like you can with the old NMOS, is there? I think that RESET could un-JAM my old Synertek without waiting for SYNC, but you're simulating CMOS behavior, so you should be safe.

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Got a kilobyte lying fallow in your 65xx's memory map? Sprinkle some VTL02C on it and see how it grows on you!

Mike B. (about me) (learning how to github)

There are no undefined states in the state machine, and no loops, so it should always return to the SYNC state within a handful of cycles, even if the rest of the design is in a random state.

This is looks very promising. I'm looking forward to it being integrated back into the main core and being able to try it out in the Beeb.

Dave

The disassembly/state output in ASCII is very convenient when you're looking at the simulation traces.

(the STP instruction is not supported by the core, I use it to $finish the sim)

I spent some time yesterday fidding with the Beeb Accelerator design (which is currently using Arlet's original design, with the BigEd/Hoglet C02 extentions).

I spotted a couple of signals in Beeb Accelerator that looked like they could be pipelined, and this improved the maximum clock speed from 80MHz to 90MHz. This didn't involve any CPU core changes at all.

The critical paths then seem to be a mix of:
- Block RAM => DI => ALU (passing through the BCD logic) => Carry Out Register
- Block RAM => DI => ABL/ABH => nextAddress => Block RAM

I was wondering if there was any merrit in exploring an ALU design that makes use of the DSP48A slice? Or is this obviously a non-starter?

https://www.xilinx.com/support/document ... /ug389.pdf

Clearly the BCD path would need to be seperate, and this may be the stumbling block. But in the C02 there is an extra cycle available for BCD anyway, isn't there?

Dave

Yes, the new C02 uses an additional BCD cycle. I think a bigger problem is that the DSP block doesn't do logic operations (AND,OR,EOR) which are currently integrated in the adder. You might get a little faster carry, but that's probably wiped out by the extra layer of logic.

In the WDC 65C02, there is a STP instruction which halts the CPU - it won't even respond to interrupts - until a Reset arrives. It's not quite the same as the "jam" opcodes on the NMOS version; STP is deliberately programmed into the microcode.