I am in the process of debugging one of my first 6502 projects and am having some flakey issues (mostly stupid stuff I did in layout); However, I read somewhere that there is a limit of one TTL load that can be put on the 6502 address buss for address lines A8-A15, but that A0-A7 can have multiple TTL loads.
When I read the data sheet for the 6502, it does not say this, but it does not really say what the maximum loading can be!
Also, would the 65C02 have the same loading restrictions?
Jim Knight
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Number of gates that can be put on 6502 Address Buss
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All the address lines are the same as the data lines, 1 TTL load. LSTTL is a lot lighter, but use CMOS. The 65c02 is a little different in that it can pull up just as hard as it can pull down. Assuming you have access to the 65C02, use that one instead. It not only saves a lot of power and runs cool, but has more instructions and addressing modes, some hardware enhancements, and all the NMOS 6502 bugs are corrected on the 65c02.
Thanks - One more question?
I would assume that if I monitor the Data and Address signals and the high voltage stays up at about 4V then there is NOT a loading issue on these lines? I am actually loading down the upper addresses using HCT devices to decode for RAM/ROM/RIOT, etc.
Jim Knight
Jim Knight
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