Already a long time ago I wanted to design my own system based on a 65816. I converted some 6502 systems to 65816 but, with one exception, I didn't use the capability to handle more than 64 KB of memory. The exception, a VIC-20, worked except it crashed when I used the RDY line to debug something. FYI: the VIC-20 doesn't use it at all so nothing happened in normal operation. It took a long time to figure out what happened.

To create the address lines A16..23 I used a 74ALS573, clocked by PHI1. When I negated RDY, the 65816 halted, still outputting the data that was outputted when PHI0 was (H). This created a complete different address at A16..23 with the resulting catastrophic result. AFAIK the data sheet didn't mention this but it did mention that PHI0 could be stretched as long as needed.
So I created a circuit that stretched PHI0, and therefore PHI, when RDY was (L).



As you can see it needs seven NAND gates. I am sure it can be simplified and a GAL will take less place than two 74LS00 ICs. But a GAL has to be based on a real design before you can program it.
In short: NAND gate IC2B will output CLK as long as RDY is (H). if RDY is (L) when CLK is (L) as well, nothing will happen. When RDY is (L) when CLK is (H), the flipflop will change state and will block IC2B from that moment on. If RDY becomes (H) again before the falling edge of CLK, the fliflop will be reseted and nothing will happen again.

Of course I checked this forum and used Google to find some other designs to see how these where done but the ones I found where either just 64 KB, like Dinosaurus' POC or used GALs and CPLDs.

I would appreciate it if somebody would confirm my idea.

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Thanks for posting the circuit (which I'm not able to fully examine at the moment) but I can confirm that using RDY on an '816 with >64K isn't as simple as on an '02 or 'C02. In this thread, forum member cr1901 confirmed, "The 65816 does NOT drive the bank address while RDY is low." In other words, the Bank-Address, Data pattern that normally occupies the 816's data bus during the Phi2-low, Phi2-high periods of every cycle is suspended, and no Bank Address is driven onto the bus.

Instead of driving RDY your circuit uses clock-stretching -- a viable alternative in some situations. The pros and cons of both approaches are explored in the thread RDY vs CLOCK STRETCHING. Includes 2 very simple circuits.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

It is still possible to use RDY to halt the '816, but you have to incorporate it into the equation for latching the bank address.

Hallo Jeff,

Thank you for your thread. The problem with the 163 is that you can stretch the clock only a limited number of cycles (if I understood correctly). Unfortunately that is not enough for single stepping because we human beings are so sloooooooow.
I didn't know about this bi-directional behavior of the WDC65816 but I know for sure that the clock can be stretched indefinitely when (H). not when (L).

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Add the eighth NAND gate to the output of above schematic and you have the signal you can use for the 573 that latches the address lines A16..23. In fact that was the original design. But then came this "nice" surprise that WDC's RDY is bidirectional. It meant a 05 or 06 OC inverter instead of the last NAND gate, a gate a GAL cannot provide. If there wasn't this possibility to stretch the clock, I wouldn't have any other choice.

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As an expedient, you can put a 3K3 resistor in parallel with a small capacitor, between your RDY driver and the RDY pin. That will allow the CPU to pull it low when WAI is executed, without causing a short, and doesn't require open-collector drivers.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

First: I never liked tricks like these like using diodes to save an AND or OR gate. Then use the real part. But that is my opinion.
Second: I need this circuit anyway to control my 573 address latch so it was no trouble at all to use it for clock stretching.

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I was asked by Jeff to explain my circuit a bit more:
- the CLK signal is the signal that normally would have gone to the PHI0 input of the 65816, let's call this signal PHI0.
- the RDY signal is the signal that normally would have gone to the RDY input of the MOS 65816 but is now connected to the input of this circuit. The RDY input of the WDC 65816 is tied to +5V using a resistor.
- the CLK0 signal is the signal that now goes to PHI0 of the 65816. An inverter should create CLK1, an alternative PHI1, out of this signal and should be connected to the 573 latch.
Unless you really know what you are doing, there is no other use for CLK0 and CLK1. It is PHI0 that is tied to timers, 6522s and other ICs that do need PHI2 as input. If PHI1 is needed, it has to be generated from PHI0.

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I think I own you an explanation for this thread:

My first computer was a Commodore 64. But my first job was in a shop were we assembled PCs, mainly XT compatibles in the beginning, and I started to like them to. This resulted after years into that I decided to design two XT boards, one suitable for the original IBM 5160 and mini-AT cases and one for the still available ATX case:

Schematic: http://www.baltissen.org/images/ATX-sch.png
Board: http://www.baltissen.org/images/ATX-brd.png

FYI: the design is made in Eagle 7.7.0 and is free. And I think what I will have for Christmas

This design inspired me to to create an ATX board but then either powered by a 6502 / MMU combination or a 65816. I like the elegance of the MMU and I am still thinking of a third option, combining the 65816 with the MMU.
The MMU I have in mind, the 74LS612 is a twelve bitter. Using it in 8-bits mode only enables me to address 1 MB in chunks of 4 KB each. The 816 can address 16 MB and having an ATX board in mind with at least two 16 bits ISA slots, I think I will choose for the 65816.

The above XT has 1 MB of SRAM of which only 960 KB can be used. It has 128 KB of EEPROM of which only 64 KB can be seen at a moment but the both halves can be switched.
A 65816 starts up in 6502 mode and that means we must have access to the I/O and IMHO there should also be RAM available. In case of the 6502/MMU combination I was thinking of 64 KB of ROM but with an write through option to set the MMU so RAM etc. can be made available imediatly after a reset.

Storage: the ISA slots enable me to use PC cards and I know how to deal with IDE HDD. Here I have the choice of using real IDE HDDs but with 8 bits only, thus loosing half of their capacity (which I don't mind) or using Compact Flash cards that can be used in 8 bits mode as well. I use them as so in my XT computers. FYI: there is also the IDEXT card that enables a XT to use 16-bits IDE drives. So no problem here IMHO.
Using floppy drives should be possible as well. I have been inspired by this peripheral: http://news.ide64.org/2018/11/floppy-drive-tib-plc-dd-001-drive-2001.html. The IC on this card is 8272/765 (or whatever these numbers are exactly) compatible and even used on some clone FDC cards.

DMA: things could be loaded more quickly (how much? no idea) I think. The only thing that comes to my mind is copying the DMA circuit from the XT.

Interrupt controller: I think we can forget about using a 8259. Yesterday I found an old thread about combing a 8259 with a 6502 and here I found my own solution: read the various INT lines using a buffer, for example a 74541, invert them all, AND all the inverted signals and feed the results to the IRQ input of the 65xxx.

Video: In the past I built an interface that enabled me to attach ISA cards to my C64. MDA and CGA worked without any problem then so should do so with this design. But MDA and CGA are out of date and it should be at least VGA IMHO. But PC cards can not be used, at least I think. These cards need to be initialized and that is different for each brand. An EPROM on board of the card should be started up by the PC and that takes care of the initialization. Unfortunately a 65xxx cannot run 8ox86 binary and either some one has to find how it can be done (which most probably is different for each type of card) or we have to invent our own VGA some how.
Regarding the last I found two things:
- the Gigatron, a TTL CPU capable of VGA: https://gigatron.io/
- the TTL VGA Terminal: http://debuginnovations.com/TTL_Terminal/home.html

Keyboard: I have at least two options in my mind:
- using the the keyboard interface of the XT. Adding an 8-pins PIC enables me to connect a PS/2 keyboard. Advantage: known stuff plus some free I/O pins from the 8255. Disadvantage: bigger than the next option.
- using the 8042 keyboard interface from the IBM AT or equivalent. Disadvantage: never used. Advantage: it looks as simple as just adding a 6522 or other I/O IC. The newer HT6542 or JetKey can handle a PS/2 mouse as well. It is smaller than the XT circuit and has still a few free I/O bits.

RTC: on board.

I/O: IMHO for any other I/O we can use PC cards. If you have a special wish, not on the board but create a new card!

Timer: having no 6522 or equivalent on board so far means we have no timer. My first idea was to use a 8253 or 8254 but then, why not using a 6522 at all? It also means we have some I/O pins available for what ever. In most weird case four of them could serve as the extra needed four bits for the MMU, meaning, the 6502/MMU can handle 16 MB as well.

Frequency: I have no idea at what speed it will run. But I don't mind if it only runs at 4 MHz. (I found this thread, "Techniques for reliable high-speed digital circuits", but haven't found the time yet to read it)

Please shoot, give your comments, ideas, criticism or what ever and let's have fun with it. If things go fine, I know what my second Christmas present will be

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Or, instead use a 74HC540 or 74AC540 and avoid having to use the inverter. That's what I use in my POC V1.2 unit to make the four UART channel IRQs available to the 65C816.


My only concern with your proposed design is your choice of logic family. Using 74LS (TTL) logic will potentially create problems due to relatively weak fanout and noise immunity. I would consider CMOS for this project. In unavoidable cases where a TTL device's output must drive a CMOS input the CMOS device should be 74HCT or similar.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Or, instead use a 74HC540 or 74AC540 and avoid having to use the inverter. That's what I use in my POC V1.2 unit to make the four UART channel IRQs available to the 65C816.[/quote]
The idea is to use a 541 to read the state of the individual interrupt lines into the data bus. So without polling every attached device, the CPU can see in almost one eyblink which device is causing the interrupt. Parallel to this 541 a bunch of 7406s is used to invert the positive active signals of the ISA slot into negative active signals acceptable for the IRQ input. The OC outputs of the 7406s enable us just to wire all outputs together. A pull-up resistor is needed of course.


Consider it as a bad habit from the old days. If really needed, it is just a matter of renaming the part from 74LSxx to 74HCTxx or what ever flavor one likes. That is the advantage of an EDA.

I started to read the thread "Techniques for reliable high-speed digital circuits" and was a bit shocked. What all has to be done to make things fast in a reliable way! There was only one light in the dark for me: I checked various XT clone turbo boards and many of them were just two layers, no plane filling and no terminators. So there is still hope for this and the XT designs

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The '540 is a '541 with inverting outputs. I use it in my POC unit in the same fashion as you plan to do.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!