65816 Addressing modes and cycle counts.

[lenkki]

I have a few questions about the addressing modes of the 65816 MCU.

1) Is there any difference in the operation between the following modes:
E=1, X=1, M=1 and E=0, X=1, M=1 ?

2) I understand that I can move the "zero-page" to a arbitrary location even in Emulation mode.
Say that I have D = 0x1080 , I do an instruction with direct,indexed, x mode with the direct offset being 0xF0 and X = 0x0F
Will the addressed memory be:
0x117F ( D + offs + X)
or
0x107F (wraped inside the page)

3) I have looked at the WDC documentation for 65816 (August 4th 2008) and I found gross errors in the opcode table and the logical explanation of some of the opcodes is just plain wrong. In addition some section of the text simply make no sense no matter how many times I read them. The errors I have found make me doubt the overall accuracy of the document. The documentation from GTE ( cmd_g65sc802_g65sc816.pdf) is as far as I can see free from obvious factual errors but doesn't go to deep into the specifics of the operation during emulation and or X/M flags set to 1. What other documents would you recommend? I have no problems with the techincal yargon aslong as it's written in clear english...

To examplify: From WDC 4th aug 08:

Quote:

8.2.1 The Direct Addressing modes are often used to access memory registers and pointers.
The effective address generated by Direct; Direct,X and Direct,Y addressing modes will always be in the
Native mode range 000000 to 00FFFF. When in the Emulation mode, the direct addressing range is
000000 to 0000FF, except for [Direct] and [Direct],Y addressing modes and the PEI instruction which will
increment from 0000FE or 0000FF into the Stack area.
8.2.2 When in the Emulation mode and DH is not equal to zero, the direct addressing range is
00DH00 to 00DHFF, except for [Direct] and [Direct],Y addressing modes and the PEI instruction which will
increment from 00DHFE or 00DHFF into the next higher page.
8.2.3 When in the Emulation mode and DL in not equal to zero, the direct addressing range is
000000 to 00FFFF.

So what they're saying is that in native mode 00-0000 to 00-FFFF is addressable and in emulation mode 0000 to 00FF is addressable if the high byte is zero otherwise DH00 to DHFF is addressable if it's non-zero. How is that any different from 0000 to FFFF being addressable depending on how the D register is set?

[jerryp]

The book "Programming the 65816" by Eyes and Lichty is a good reference.

1. Differences between emulation-mode vs. native all-8-bit mode:

• - interrupts have unique vectors for each mode
  - native IRQ has its own vector, therefore there is no "B" bit in the status register in native mode
  - instruction timing differs. Address calculations that took an extra
  cycle on the 6502 for page-crosses no longer do in native mode
  - block-move instructions are sort of useless in emulation mode
  - direct-page indexed modes cross into next page in native mode;
  they wrap in emulation mode
  - interrupts in native mode set decimal mode flag D=0
  - stack is always in page 1 in emulation mode
  - TCS in emulation mode only transfers low 8-bits to S, while in
  native mode it always transfers 16-bits, regardless of the M bit

2. Indexed direct-page accesses will wrap in emulation mode.

[kc5tja]

lenkki wrote:

1) Is there any difference in the operation between the following modes:
E=1, X=1, M=1 and E=0, X=1, M=1 ?

Unless the instructions fundamentally act differently between the 65C02 and 65C816 in native mode, no. The E bit will not affect cycle timing.

Quote:

2) I understand that I can move the "zero-page" to a arbitrary location even in Emulation mode.
Say that I have D = 0x1080 , I do an instruction with direct,indexed, x mode with the direct offset being 0xF0 and X = 0x0F
Will the addressed memory be:
0x117F ( D + offs + X)
or
0x107F (wraped inside the page)

0x117F; however, my reference manual says that the D register will be hardwired to zero in emulation mode, so if my book is correct, you'll end up accessing 0x017F, which is correct from a 65C02's point of view.

This might be a bug in my documentation; Garth, can you clarify this based on your experiences with the chip?

Quote:

3) I have looked at the WDC documentation for 65816 (August 4th 2008) and I found gross errors in the opcode table and the logical explanation of some of the opcodes is just plain wrong. In addition some section of the text simply make no sense no matter how many times I read them. The errors I have found make me doubt the overall accuracy of the document. The documentation from GTE ( cmd_g65sc802_g65sc816.pdf) is as far as I can see free from obvious factual errors but doesn't go to deep into the specifics of the operation during emulation and or X/M flags set to 1. What other documents would you recommend? I have no problems with the techincal yargon aslong as it's written in clear english...

I've never found any issues with the opcode descriptions in any recent documents. Indeed, the D-register issue raised earlier would be the first I've discovered. However, since all of my work uses native-mode operation (I never use emulation mode except for boot-strapping purposes), this doesn't affect me.

Quote:

8.2.3 When in the Emulation mode and DL in not equal to zero, the direct addressing range is
000000 to 00FFFF.

Oooooooookaaaaaayyyyy.....

That IS quite strange.

I admit that my book doesn't say this. My book is much older than your copy though, and appears to go under a different title and author all-together.

Quote:

So what they're saying is that in native mode 00-0000 to 00-FFFF is addressable and in emulation mode 0000 to 00FF is addressable if the high byte is zero otherwise DH00 to DHFF is addressable if it's non-zero. How is that any different from 0000 to FFFF being addressable depending on how the D register is set?

It's not -- logically speaking, all such predicates, when OR-ed together, yield a range covering the entirety of bank 0.

[GARTHWILSON]

Quote:

0x117F; however, my reference manual says that the D register will be hardwired to zero in emulation mode, so if my book is correct, you'll end up accessing 0x017F, which is correct from a 65C02's point of view.

This might be a bug in my documentation. Garth, can you clarify this based on your experiences with the chip?

The top of page 51 of my Lichty & Eyes programming manual (near the top of page 45 on the online one, on the second page of chapter 4, second sentence under "Power-On Status: 6502 Emulation Mode") says, "The stack is confined to page one, just like the 6502 stack pointer."

Although I've never tried that part of the 816's operation (or in my case, the 802's), and although I have found a lot of errors in the WDC data sheet, I have not found any errors in the programming manual. I have a fair amount of notes in mine, but I don't remember any of them being corrections.

[lenkki]

So if I understood the programmers manual correctly, when using the DP,X in emulation mode the address would be

EA = (0x00DHDL + (offset + X)0xFF ) & 0x00FFFF

And in native mode

EA = (0x00DHDL + offset + X ) & 0x00FFFF

(X 8/16 bit as per the X flag)

And in general with the emulation flag as a parameter.
EA = (0x00DHDL + (offset +X) & (0xFF | (0xFF00*(!E))) ) 0x00FFFF

[kc5tja]

Based on my experience, it is always EA = (0x00DHDL + 0x0000XL) & 0x00FFFF. Remember that XH, YH, and SH are hard-wired to 0 in emulation mode. (In fact, if you change the mode of the CPU from native-mode to emulation mode and back again, you'll find X, Y, and S registers with the upper bytes cleared.)

[lenkki]

Ok I've solved all issues I had except for a few which I have based upon assumptions that emulation mode will indeed behave like a fixed 6502.

For example Absolute indexed modes will not cross bank boundaries as they can do in native mode.

In general is it a fair assumption that no addressing mode will cross a bank boundary in emulation mode? (They may address different banks but no indexed mode will overflow into the next bank)

[TMorita]

lenkki wrote:

...
In general is it a fair assumption that no addressing mode will cross a bank boundary in emulation mode? (They may address different banks but no indexed mode will overflow into the next bank)

The 65816 is emulating a 65C02 in emulation mode.

The 65C02 can only address 64k of memory.

Toshi

[dclxvi]

I don't have any actual 65816 hardware with me at the moment to verify what I've written below, but if my notes are correct:

You know about page zero wrapping on the 65c02 right? i.e.

LDX #1
LDA $FF,X

actually reads address $0000 not address $0100. The 65816 has a similar feature in emulation mode. When DL is zero, then the direct page (as it is now know on the 65816) wraps on a page boundary. For example,

PEA #$3400
PLD
SEC
XCE
LDX #1
LDA $FF,X

reads from address $3400. However, when DL is not zero, there is no page boundary wrapping. For example

PEA #$3401
PLD
SEC
XCE
LDX #1
LDA $FF,X

reads from address $3501, not address $3401.

Exceptions are "new" ("new" means they aren't present on the 65C02)instructions and/or addressing modes, like PEI or [dp] addressing.

In native mode, there ain't no such animal as page boundary wrapping.

Similarly, in emulation the stack is confined to page 1 (not page 0, which I'm sure is what kc5tja meant to write), again with the exception of "new" instructions and/or addressing modes.

In emulation or native mode, the direct page and the stack are confined to bank 0, i.e. the wrap at the bank boundary. Other addressing modes may cross bank boundaries. For example:

PEA #$0000
PLB
PLB
LDX #1
LDA $FFFF,X

reads address $010000, not address $000000, in both emulation and native mode. This is one of the rare instances in which a 65816 in emulation mode actually does something different than a 65C02 (or an NMOS 6502).

The caveats section in the datasheet actually lists the 65802 caveats and can be somewhat confusing, even though much of it is still true of the 65816.

In general, it can be useful to keep in mind that datasheets (for any device by any manufacturer) are usually not tutorials. They often contain information about subtle behavior of the device, but this is often somewhat cryptically stated in a single sentence or a test parameter value. Seemingly impenatrable statements are often hints regarding subtle details or special cases. This can be frustrating, as you often have to experiment as well as consult the datasheet to understand the behavior.

I guess that's the long way of saying WDC's documentation is for the most part pretty good, but they have errors here and there like anyone else (and it could be clearer at times).

[kc5tja]

dclxvi wrote:

Similarly, in emulation the stack is confined to page 1 (not page 0, which I'm sure is what kc5tja meant to write)

Correct; SH is hardwired to $01, not to $00. Typo on my part.

[lenkki]

TMorita's and dclxvi's posts are contradicting. I interpret TMorita's post such that my assumption would hold but dclxvi's post states that it will not allways hold. Which is it ?

[kc5tja]

They are not contradictory. TMorita's claim concerns emulation mode only. Except for 65816-specific opcodes and addressing modes, the 65816 will faithfully emulate a 65C02 in emulation mode. In other words, if you write your software to run on a 65C02, it will not be able to tell it's running on a 65816 unless it compares expected results when using a 65C02-specific or 65816-specific instruction.

[dclxvi]

lenkki wrote:

TMorita's and dclxvi's posts are contradicting. I interpret TMorita's post such that my assumption would hold but dclxvi's post states that it will not allways hold. Which is it ?

I would strongly encourage you to try my code (or some variation of it) and see what happens on an actual 65816 rather than just simply taking my word for it. Again, I'm working from notes (and my own memory) here; I think it what I am claiming above is correct, but I have no way of verifying it at the moment, and it's possible that I could be mistaken.

[lenkki]

I would love to try my hands on a real 65816 but I don't have the hardware. I'm trying to emulate one you see.

[mrkite]

I can verify that Applesoft BASIC, line $EA9B (STA RESULT+3,X) relies on zero page wrapping in emulation mode since X is negative.