My project with a w65c265s MCU.

[BitWise]

The PCS register determines which bits of PD7 are chip selects. The Mensch monitor initialises it at power up when it checks for external ROMs. I don't think all the selects are enabled by default.

The '265 contains logic that looks at the target 24-bit memory address and works out which area it is trying to access. It sets the appropriate chip select low (e.g. GND) if the access is in externally configured memory. If its handled by an internal ROM, RAM or peripheral register the chip selects will be high (+5V).

Chip selects are active low so the LED powered from +5V via a load resistor will light when the corresponding memory areas is accessed.

The '265 has no idea if RAM or ROM is present in any of the area. The external circuitry takes as many address bits as its needs, the data bus, a chip select, the clock (PHI2) and the WEB signal (same as R/W on 6502) and uses them as required.

The 265SXB uses 3 NAND gates to combine WEB with PHI2 and create MEMOEB/MEMWEB the output enable (e.g. read) and write enable (e.g. write) signals for the RAM and FLASH chips which use CS3B and CS4B as thier chip select signals.

[Dr Jefyll]

tokafondo wrote:

I'm working with 3.3V instead of 5V as the schematics are shown, and I like to know if the RESISTOR values should be modified.

Yes, you'll probably want to use lower values for the resistors that're in series with LEDs. Otherwise you'll notice reduced brightness. (But that's harmless, of course.)

[tokafondo]

BitWise wrote:

The PCS register determines which bits of PD7 are chip selects. The Mensch monitor initialises it at power up when it checks for external ROMs. I don't think all the selects are enabled by default.

Well. For a start, the datasheet states that

Code: Select all

Address   Label   Function              Reset Value
00:DF27   PCS7    Port 7 Chip Select    $00
00:DF23   PD7     Port 7 Data Register  $FF

But after a reset, in my chip

Code: Select all

00:DF23 = $04 = %00000100
00:DF27 = $FB = %11111011

So then, AFAIK, CS2B is OUTPUT as set in DF23, and ACTIVE as set in DF27, isn't it?

BitWise wrote:

The '265 has no idea if RAM or ROM is present in any of the area. The external circuitry takes as many address bits as its needs, the data bus, a chip select, the clock (PHI2) and the WEB signal (same as R/W on 6502) and uses them as required.

So it should be as easy as wiring the memory chip, and have P73_CS3B_SRAM connected to the /CE input of the chip, shouldn't it? And then, every write to the memory area of 00:0200 - 00:7FFF should be done on the chip, shouldn't it?

And all of that, with no tinker at all with $00:DF23, $00:DF27 or SSCR registers...

Well, it doesn't work. It seems I'll have to carefully test every DATA, ADDRESS, /CE, /WE and /OE line between the '265 and the AS6C1008.

I also replaced the 560nf capacitor with a 1uf one, because I'm working with a lower voltage here... should it change anything?

Thanks, again.

[tokafondo]

Dr Jefyll wrote:

tokafondo wrote:

I'm working with 3.3V instead of 5V as the schematics are shown, and I like to know if the RESISTOR values should be modified.

Yes, you'll probably want to use lower values for the resistors that're in series with LEDs. Otherwise you'll notice reduced brightness. (But that's harmless, of course.)

I'm working with them "as is", with no resistors. Those are green LEDs.

[tokafondo]

Time to work with the logic probe. I set up the eight channels so they capture then DATA BUS.

I did a "FILL 00:0200-00:7FFF with $FF value" and recorded the stream.

And it seems the memory chip is actually getting the data.

What I'm not that sure if the timing between pulses is right... Shouldn't be done in the timing of nanoseconds instead of microseconds?

[tokafondo]

GOOD NEWS!!

I finally figured it out, with the help of Alliance Memory support team.

Maybe this is bread and butter for you, but I learned that with the AS6C1008, DIP version, CE2 must be tied to Vcc all the time, for the chip understand that it's being selected.

I left A15 and A16 tied to GND.

I also replaced the decopling capacitor from a 560nf to a 100nf one.

Chip select is tied to CS3B, as standard in the SXB.

I still haven't wired the EEPROM chip, BTW.

But...

[tokafondo]

I can't make w65c265sxb hacker master run.

I followed the README.MD instrucions but I can't get the "welcome" message displayed in the terminal windows that I setup for the extra UART. I even wired a PL2303 as recommended, and get nothing displayed.

I tested that the memory is being properly written by uploading the program to the SBC, and then reading the memory locations it get copied to. And compared it to a binary compilation of the same program.

It seems the program is there. When I do "G 00:0300", the board sometimes resets, or get frozen, though.

[tokafondo]

More on this: I examined the .ASM and .INC files and found this variable, OSC_FREQ, set to 3686400.

I changed it to 4915200, that is the FCLK running my SBC.

I also found BAUD_RATE equ 9600, and that seemed to me not to be in the same line od the README.MD file, that says that the extra UART should be configured to 19200,8N1.

But again, this doesn't work. And the code is all there in RAM.

[BitWise]

tokafondo wrote:

More on this: I examined the .ASM and .INC files and found this variable, OSC_FREQ, set to 3686400.

I changed it to 4915200, that is the FCLK running my SBC.

I also found BAUD_RATE equ 9600, and that seemed to me not to be in the same line od the README.MD file, that says that the extra UART should be configured to 19200,8N1.

But again, this doesn't work. And the code is all there in RAM.

The checked in version (and the S28) is configured to take over the serial line from the monitor so I'd leave it at 9600. I just booted up my copy and it outputs this:

Code: Select all

MENSCH ROM Version 2.07
 (C) Copyright 1995
Assembled Mon Feb  6 10:03:42 1995

PCntr     Acc    Xreg   Yreg   Stack
00:E358   00 00  E0 B7  00 FF  01 FF

  DirRg  F  DBk
  00 00  22 00


Status Reg
N  V  M  X  D  I  Z  C
0  0  1  0  0  0  1  0

>S  .0001.0002.0003.0004.0005.0006.0007.0008.0009.0010.0011.0012.0013.0014.0015.
0016.0017.0018.0019.0020.0021.0022.0023.0024.0025.0026.0027.0028.0029.0030.0031.
0032.0033.0034.0035.0036.0037.0038.0039.0040.0041.0042.0043.0044.0045.0046.0047.
0048.0049.0050.0051.0052.0053.0054.0055.0056.0057.0058.0059.0060.0061.0062.0063.
0064.0065.0066.0067.0068.0069.0070.0071.0072.0073.0074.0075.0076.0077.0078.0079.
0080.0081.0082.0083.0084.0085.0086.0087.0088.0089.0090.0091.0092.0093.0094.0095.
0096.0097.0098.0099.0100.0101.0102.0103.0104.0105.0106.0107.0108.0109.0110.0111.
0112.0113.0114.0115.0116.0117.0118.0119.0120.0121.0122.0123.0124.0125.0126.0127.
0128.0129.0130.0131.0132.0133.0134.0135.0136.0137.0138.0139.0140.0141.0142.0143.
0144.0145.0146.0147.0148.0149.0150.0151.0152.0153.0154.0155.0156.0157.0158.0159.
0160.0161.0162.0163.0164.0165.0166.0167.0168.0169.0170.0171.0172.0173.0174.0175.
0176.0177.0178.0179.0180.0181.0182.0183.0184.0185.0186.0187.0188.0189.0190.0191.
0192.0193.0194.0195.0196.0197.0198.0199.0200.0201.0202.0203.0204.0205.0206.0207.
0208.0209.0210.0211.0212.0213.0214.0215.0216.0217.0218.0219.0220.0221.0222.0223.
0224.0225.0226.0227.0228.0229.0230
READY
>g
Enter Address  BB:AAAA 00:0300

W65C265SXB-Hacker [18.06]
.?
B bb           - Set memory bank
D ssss eeee    - Disassemble memory in current bank
E              - Erase ROM area
F 0-1          - Disable/Enable WDC ROM
H              - Hunt for RAM
G [xxxx]       - Run from bb:xxxx or invoke reset vector
M ssss eeee    - Display memory in current bank
R 0-3          - Select ROM bank 0-3
S...           - Process S19 record
W xxxx yy      - Set memory at xxxx to yy
X xxxx         - XMODEM receive to bb:xxxx
.

The only change to the source you should have to make is the OSC_FREQ setting.

[BitWise]

The README.md needs some correction.

Originally the hacker tool communicated with UART0 at 19200 via a second serial connection but I later changed the code so its uses the connection indicated by the value of the UART symbol in w65c265sxb.asm at the BAUD_RATE define in the same area.

The checked in code uses the UART 3 at 9600 baud which is the same as the built in monitor.

I'll update the README.md to reflect this.

Its good to get confirmation that the '265 runs at higher speeds that 3.84MHz. I bought some '265s intending to build a board with an 8Mhz or higher oscillator. The monitor doesn't work above 6Mhz but it will still boot into a ROM if it finds the WDC signature.

[tokafondo]

Thanks. Does it boot with no ROM chip installed?

[BitWise]

tokafondo wrote:

Thanks. Does it boot with no ROM chip installed?

Should do. Its a RAM based application.

[tokafondo]

It's ALIVE!!!!

Code: Select all

MENSCH ROM Version 2.07
 (C) Copyright 1995
Assembled Mon Feb  6 10:03:42 1995

PCntr     Acc    Xreg   Yreg   Stack
00:E358   00 00  E0 B7  00 FF  01 FF

  DirRg  F  DBk
  00 00  22 00


Status Reg
N  V  M  X  D  I  Z  C
0  0  1  0  0  0  1  0

>S  .0001.0002.0003.0004.0005.0006.0007.0008.0009.0010.0011.0012.0013.0014.0015.
0016.0017.0018?.0019.0020.0021.0022.0023.0024.0025.0026.0027.0028.0029.0030.0031
.0032.0033.0034.0035.0036.0037.0038.0039.0040.0041.0042.0043.0044.0045.0046.0047
.0048.0049.0050.0051.0052.0053.0054.0055.0056.0057.0058.0059.0060.0061.0062.0063
.0064.0065.0066.0067.0068.0069.0070.0071.0072.0073.0074.0075.0076.0077.0078.0079
.0080.0081.0082.0083.0084.0085.0086.0087.0088.0089.0090.0091.0092.0093.0094.0095
.0096.0097.0098.0099.0100.0101.0102.0103.0104.0105.0106.0107.0108.0109.0110.0111
.0112.0113.0114.0115.0116.0117.0118.0119.0120.0121.0122.0123.0124.0125.0126.0127
.0128.0129.0130.0131.0132.0133.0134.0135.0136.0137.0138.0139.0140.0141.0142.0143
.0144.0145.0146.0147.0148.0149.0150.0151.0152.0153.0154.0155.0156.0157.0158.0159
.0160.0161.0162.0163.0164.0165.0166.0167.0168.0169.0170.0171.0172.0173.0174.0175
.0176.0177.0178.0179.0180.0181.0182.0183.0184.0185.0186.0187.0188.0189.0190.0191
.0192.0193.0194.0195.0196.0197.0198.0199.0200.0201.0202.0203.0204.0205.0206.0207
.0208.0209.0210.0211.0212.0213.0214.0215.0216.0217.0218.0219.0220.0221.0222.0223
.0224.0225.0226.0227.0228
READY
>g
Enter Address  BB:AAAA 00:0300

W65C265SXB-Hacker [18.06]
.?
B bb           - Set memory bank
D ssss eeee    - Disassemble memory in current bank
E              - Erase ROM area
F 0-1          - Disable/Enable WDC ROM
H              - Hunt for RAM
G [xxxx]       - Run from bb:xxxx or invoke reset vector
M ssss eeee    - Display memory in current bank
R 0-3          - Select ROM bank 0-3
S...           - Process S19 record
W xxxx yy      - Set memory at xxxx to yy
X xxxx         - XMODEM receive to bb:xxxx
.h
00:0000-00:7FFF
.

[tokafondo]

Well... I'm very happy because I finally got the board to use an external power supply. I originally used the SXB design, that get its power from the USB port. But now I put two voltage regulators. One from "more or less anything" down to 6V. And then, below that one, down to ~3.3v.

Why this? Because the graphic chip will use 1.5v, so I will take that from 6V instead of 3.3v, following recommendations that the input voltage should be >2V higher than the output voltage.

Also, I got installed a second 128K RAM chip.

[tokafondo]

Well. I attached as second 128K SRAM chip and connected /CE to the CS5B pin in the '265s. It should be the same as connecting it to the J1 connector of the '265SXB's.

And I say it should be because the J1 connector in the SXB does not have the MEMOEB and MEMWEB generated in the SXB.

But my clone uses MEMOEB and MEMWEB to feed /OE and /WE pins in this second 128K SRAM chip. I don't know if I should wire this second chip directly to PHI2 and WEB, instead of MEMOEB and MEMWEB.

Anyway:

Bitwise wrote:

The datasheet seems to suggest that you could disable CS3B generation and have the one 128K RAM chip cover $00:0000-$01:FFFF using CS5B but some regions will map to chip based memory unless you disable more signals.

I tried programming the PLD on my 1MB SRAM board to use CS5B but it didn't work and I've not had the time to work out why. I use CS7B as it works reliably.

When I fire the hacker tool, and press the H command, I get:

Code: Select all

W65C265SXB-Hacker [18.06]
.
.
.h
00:0000-00:7FFF
01:0000-3F:FFFF
.

I can't understand... The thing is that the first chip is wired to have only 32K available. That's ok.

But the second chip should have only have two banks of 64K of RAM, at 01:0000-FFFF and 02:0000-FFFF... But even that shouldn't be possible, because the datasheet states that...

'265s datasheet wrote:

When on-chip ROM, CS3B and/or CS4B are enabled, then CS5B decode is reduced by the
addresses used by same. CS0B and CS1B address space never appears in CS2B, CS4B or
CS5B decoded space.

...so in theory, I should be having available 01:0000-FFFF because 00:0000-FFFF is getting managed by the internals of the chip select.

Now. this:

Code: Select all

W65C265SXB-Hacker [18.06]
.
.
.h
00:0000-00:7FFF
01:0000-3F:FFFF
.b 1
.w 0000 00
.W 0001 01
.W 0002 02
.W 0003 03
.W 0004 04
.W 0005 05
.W 0006 06
.W 0007 07
.W 0008 09
.W 0009 09
.W 000A 0a
.W 000B 0b
.W 000C
.?
B bb           - Set memory bank
D ssss eeee    - Disassemble memory in current bank
E              - Erase ROM area
F 0-1          - Disable/Enable WDC ROM
H              - Hunt for RAM
G [xxxx]       - Run from bb:xxxx or invoke reset vector
M ssss eeee    - Display memory in current bank
R 0-3          - Select ROM bank 0-3
S...           - Process S19 record
W xxxx yy      - Set memory at xxxx to yy
X xxxx         - XMODEM receive to bb:xxxx
.m 0000 000f
01:0000 00 01 02 03 04 05 06 07 09 09 0A 0B AA AA AA AA |................|
.b 2
.w 0000
.w 0000 00
.W 0001 1
.W 0002 2
.W 0003 3
.W 0004 4
.W 0005 5
.W 0006 6
.W 0007 7
.W 0008 8
.W 0009 9
.W 000A a
.W 000B b
.W 000C c
.W 000D d
.W 000E e
.W 000F f
.W 0010 g
.m 0 f
02:0000 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F |................|
.b 3
.w 0 0
.W 0001 1
.W 0002 2
.W 0003 3
.W 0004 4
.W 0005 5
.W 0006 6
.W 0007 7
.W 0008 8
.W 0009 9
.W 000A
.m 0 f
03:0000 00 01 02 03 04 05 06 07 08 09 0A 0B AA AA AA AA |................|
.b 4
.w 0 0
.W 0001 1
.W 0002 2
.W 0003 3
.W 0004 4
.W 0005 5
.W 0006 6
.W 0007 7
.W 0008 8
.W 0009 9
.W 000A
.m 0 f
04:0000 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F |................|
.b 5
.w 0
.w 0 0
.W 0001 1
.W 0002 2
.W 0003 3
.W 0004 4
.W 0005 5
.W 0006 6
.W 0007 7
.W 0008 8
.W 0009 9
.W 000A
.m 0 f
05:0000 00 01 02 03 04 05 06 07 08 09 0A 0B AA AA AA AA |................|
.b 6
.w 0 0
.W 0001 1
.W 0002 2
.W 0003 3
.W 0004 4
.W 0005 5
.W 0006 6
.W 0007 7
.W 0008 8
.W 0009 9
.W 000A
.m 0 f
06:0000 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F |................|
.

I've changing banks from 0 to 6, and when I write values for it, and then read them out... they show, even being banks that should be able to be read from, because they are outside the range of memory I actually have wired.

Why is this happening? What are I'm missing?