State of W65C02 when BE is kept low ?

[Agrimensor]

Hi,

I'm wondering what happens with W65C02 when BE is low.
Does the microprocessor preserve the status of its registers so that execution can be reasumed when BE is put back to HIGH ?

I have one W65C02 free spinning with data bus connected to NOP (EA) and a pushbutton to control the state of BE.
For what I have observed, it seems that the micro preserves its state if clock is stopped, but otherwise it keeps advancing the execution (but with the adress bus in high impedance) and reading NOP instructions in my setup.
In a realistic configuration, it would probably read random instructions from memory.

So, if I want to write on the memory with an external device and then reassume execution, I also have to stop the clock. Is it so ?

Thanks !!

[drogon]

Agrimensor wrote:

Hi,

I'm wondering what happens with W65C02 when BE is low.
Does the microprocessor preserve the status of its registers so that execution can be reasumed when BE is put back to HIGH ?

I have one W65C02 free spinning with data bus connected to NOP (EA) and a pushbutton to control the state of BE.
For what I have observed, it seems that the micro preserves its state if clock is stopped, but otherwise it keeps advancing the execution (but with the adress bus in high impedance) and reading NOP instructions in my setup.
In a realistic configuration, it would probably read random instructions from memory.

So, if I want to write on the memory with an external device and then reassume execution, I also have to stop the clock. Is it so ?

Thanks !!

Quite simply; when you pull BE low, it tristates all 16 address bus lines and all 8 data bus lines.

And that's all.

R/W is not tristated, so you may wish to isolate that somehow. The clock doesn't stop, Rdy stays as it is.

So all it does is tristate the buses - this means that unless you have stopped it (stopped the clock or pulled Rdy low) then the 65C02 will read garbage and likely crash.

I use BE in my 6502/65816 designs, so I can have a block of shared RAM with another processor, but I also stop the CPU with a WAI instruction.

-Gordon

[BigEd]

(welcome, Agrimensor... I was composing a reply but it would now be redundant!)

[daniMolina]

Actually, RW is also tristated in wdc CPUs at least.

[drogon]

daniMolina wrote:

Actually, RW is also tristated in wdc CPUs at least.

Hm. It didn't seem like it in my initial testing however... (Not an issue for me as I feed it through a GAL to generate separate /Rd and /Wr signals that need separating from the ones coming from the other processor anyway)

Cheers,

-Gordon

[Chromatix]

Put simply - BE takes the CPU off the bus, RDY lets you halt the CPU on a cycle by cycle basis. They are two separate functions on the 6502. If you mess it up, you can seriously confuse the CPU.

One use of BE that doesn't require halting the CPU is using the Phi1 phase of the bus cycle for DMA, for example to feed the video display. You won't see early micros using BE for this purpose, simply because early 6502s didn't have it; they had to insert multiplexers instead.

[BigDumbDinosaur]

drogon wrote:

R/W is not tristated, so you may wish to isolate that somehow.

RWB is tristated. That is stated on page 9 of the data sheet.