My guess is that the C02, like the 02, does not initialise the stack pointer. Do you have a reference showing that the stack pointer is initialised on the C02?
Edit: visual6502 doesn't have any way to show undefined state - all of the 6502 state except PC should be undefined at reset. The apparent initial values should not be read as meaningful.
65C02 in verilog - extended version of Arlet's core
Re: 65C02 in verilog - extended version of Arlet's core
Part of a standard 6502 reset handler is LDX #$FF : TXS. Is that what you tried?
Re: 65C02 in verilog - extended version of Arlet's core
No I only have http://visual6502.org/JSSim/expert.html which shows SP:fd after you "reset" it. You can change the reset vector with a parameter (so the first state shown is apparently after reset vectors are read and a "JMP" to that vector). There is no documentation on any reset handler happening in the shadows, so this is what state the simulation gives the stack pointer as an initial value.
It could be that the simplistic model of the capacitance in this simulation is what gives this stack pointer state. Unless its actually forced there by some internal component/handler on the chip. I don't know the model well enough to say that either are true.
It could be that the simplistic model of the capacitance in this simulation is what gives this stack pointer state. Unless its actually forced there by some internal component/handler on the chip. I don't know the model well enough to say that either are true.
Re: 65C02 in verilog - extended version of Arlet's core
Indeed, the model only has binary, so there's simply no way for it to handle or display uninitialised state. The reason for the fd is almost surely what happens in the few pre-initialisation cycles which the simulation does before it reaches time zero. There's nothing scientific or especially realistic about those, I think, it's just what was empirically necessary to get the machine to the point where it could run programes.
The initial states of A, X, Y, S, and P are all arbitrary and not to be taken as definitive or indicative.
There's a tactic sometimes used in chip simulation of seeding all the state randomly, so each run will come out different, except for any state which really is reset.
The initial states of A, X, Y, S, and P are all arbitrary and not to be taken as definitive or indicative.
There's a tactic sometimes used in chip simulation of seeding all the state randomly, so each run will come out different, except for any state which really is reset.