ATF15xx Verilog/VHDL using Quartus 13.0 SP1

LIV2 · Post by **LIV2** » Tue Feb 04, 2020 7:25 pm

Just thought I'd share some info I was given recently that ATF15xx CPLDs are pin & code compatible with the Altera MAX 7000 Series
It even says so on the microchip website: https://www.microchip.com/design-center ... plds-cplds

I thought this was awesome because it means we still have access to new 5V parts that can be programmed using Verilog/VHDL & don't cost a fortune

What you'll need:

Quartus 13.0 SP1 & MAX II, MAX V, MAX 3000, MAX 7000 device support files
POF2JED and ATMISP

When creating the design in Quartus make sure to select the corresponding EPM7XXX device and the correct package/voltage

After you compile your design in Quartus you should have a .POF file in your output_files folder which you can convert to a compatible JED file using POF2JED, It's probably best to set JTAG mode to ON in POF2JED unless you wish to never program the device again
The resulting JED can be programmed using ATMISP and an ATDH1150 cable, or use ATMISP to convert that to an SVF file which can be programmed using OpenOCD/urJTAG and any cable supported by them.

I have tested by swapping an EPM7128S with an ATF1508AS and it works perfectly

There is a an (old) cross reference of Atmel > Altera CPLDs here but basically it seems that:
ATF1502AS == EPM7032S
ATF1504AS == EPM7064S
ATF1508AS == EPM7128S

ElEctric_EyE · Post by **ElEctric_EyE** » Tue Feb 04, 2020 10:55 pm

That is some great info! We really need more people to get into programmable logic. I mean retro is retro, but retro-mod is really where it's at IMO.

jds · Post by **jds** » Wed Feb 05, 2020 9:55 pm

I had been using the Atmel tools to program the ATF1508AS with Verilog and they worked quite well. It was very sensitive to pin assignment which was a bit of a hassle once you have a board set up, but otherwise it worked well. I had a small boot ROM in the 1508 so I was pushing the limits of what I could fit in there. I had a license for these tools, but when I asked about renewing it they suggested using Quartus as above. I’ve downloaded but haven’t tried it out yet.

I was trying to do this all in Linux as I don’t have windows, but I don’t think that is currently possible. From memory I had POF2JED for Linux, but still needed ATMISP on windows.

cbscpe · Post by **cbscpe** » Sat Apr 04, 2020 6:24 am

I'm still using all retro, that is a Windows XP in a VM with WinCUPL and ATMISP. But sometimes I wished I could avoid this Windows XP. So one question, does ATMISP work on Windows 10? I did not have much success. So what is the trick?

DerTrueForce · Post by **DerTrueForce** » Sat Apr 04, 2020 8:15 am

it does kinda work, but I find it more expedient(and less crash-prone) to ignore the GUIs and just use the command-line tools they back onto directly. Finding the docs for them might be a little painful, and the help files WinCUPL comes with are actually fairly helpful for this.

cbscpe · Post by **cbscpe** » Sat Apr 04, 2020 9:03 am

Does that mean there is a command line equivalent for ATMISP? I was not aware of this. Which is it?

DerTrueForce · Post by **DerTrueForce** » Sat Apr 04, 2020 10:42 pm

I wasn't talking about ATMISP, I was talking about WinCUPL.
I can't speak to ATMISP, I never ended up using it. But it does support the USB programmer, so it should probably "just work" on win10.

LIV2 · Post by **LIV2** » Mon Apr 06, 2020 1:40 pm

I've been using ATMISP under Windows 10 but only to convert the .JED to a .SVF so I can program the CPLD with urJTAG.

Proxy · Post by **Proxy** » Mon Jun 08, 2020 5:02 pm

cbscpe wrote:

I'm still using all retro, that is a Windows XP in a VM with WinCUPL and ATMISP. But sometimes I wished I could avoid this Windows XP. So one question, does ATMISP work on Windows 10? I did not have much success. So what is the trick?

I've been using both on Win10...
while the GUI on WinCUPL is definitely a bit glitchy (which is why i only use it to actually compile programs and use NP++ to write them), it still works and does it's job fine.
ATMISP works perfectly fine, i didn't have any problems with it though i only used it twice so far...

personally to me it doesn't seem worth it to use a VM on programs that are still completely functional

cbscpe · Post by **cbscpe** » Mon Jun 08, 2020 5:16 pm

Proxy wrote:

personally to me it doesn't seem worth it to use a VM on programs that are still completely functional

In the meantime I recognized there are two versions if ATMISP one for Windows XP and another one for Windows 7 and never. I switched to a VM runnning now Windows 10 and migrated al my tools. The VM however is due to the fact that my native OS is macOS.

Proxy · Post by **Proxy** » Mon Jun 08, 2020 5:42 pm

cbscpe wrote:

In the meantime I recognized there are two versions if ATMISP one for Windows XP and another one for Windows 7 and never. I switched to a VM runnning now Windows 10 and migrated al my tools.

ye, it should be a bit better on Win10 as well just by being a newer OS.

cbscpe wrote:

The VM however is due to the fact that my native OS is macOS.

oh i see, i assume it's for work reasons or similar? otherwise you could just install Win10 as the native OS and not have to deal with any VM to run all your programs.

hoglet · Post by **hoglet** » Wed Oct 28, 2020 4:03 pm

LIV2 wrote:

I have tested by swapping an EPM7128S with an ATF1508AS and it works perfectly

I've just been trying out this design flow, and have a question for you about POF2JED.

POF2JED works fine when I'm using the 64 macro cell ATF1504AS parts, but with the 128 macrocell ATF1508AS I get the following error in the console log:

Code: Select all

***************************************************************
Error! POF Conversion may not be correct.
       Please contact to Atmel EPLD Hotline (408)436-4333, or
       email address (pld@atmel.com)
***************************************************************

It still goes on to generate a sensible looking JEDEC file, but I'd like to understand what's going on here.

Do you see this error as well?

If not, is there any chance you could upload a sample POF file that I can try out?

Dave

Martin A · Post by **Martin A** » Wed Oct 28, 2020 7:14 pm

POF from an experimental video board using the ATF1508 enclosed.

I've included the source VHDL and JED output I got from PO2JED 4.45.1 for reference

hoglet · Post by **hoglet** » Wed Oct 28, 2020 9:39 pm

Martin A wrote:

POF from an experimental video board using the ATF1508 enclosed.

I've included the source VHDL and JED output I got from PO2JED 4.45.1 for reference

That's very helpful.

I've just run your POF file through POF2JED and get the same JEDEC file as you did (except for the date).

But I still get the error logged to the console:

Code: Select all

***************************************************************
Error! POF Conversion may not be correct.
       Please contact to Atmel EPLD Hotline (408)436-4333, or
       email address (pld@atmel.com)
***************************************************************

Do you also see this error?

Martin A · Post by **Martin A** » Wed Oct 28, 2020 10:16 pm

I don't remember any errors being produced, but memory being what it is, I re-ran the conversion, and this is the log output:

Code: Select all

Microchip Pof2jed  Version 4.45.1 Mar 13 2018
Copyright 2018 Microchip. All Rights Reserved.

  EPM7128SLC84-10 --> 1508asPLCC84
Input file                : C:\altera\13.0sp1\Projects\6502Test2\output_files\6502Test2.pof
Output file               : C:\altera\13.0sp1\Projects\6502Test2\output_files\6502Test2.jed
Conversion Report file    : C:\altera\13.0sp1\Projects\6502Test2\output_files\6502Test2.txt

Conversion is completed

Options :  (1508 only)
   Powerdown :		OFF
   Security Bit :	AUTO
   Slew Rate :		AUTO
   PinClk :		OFF
   Race Coverage :	ON
   Pin Keeper :		OFF
   Macrocell Low Power:	AUTO
   Power Reset :	ALWAYS
   ITD on GCLK1 :	ON
   ITD on GCLK2 :	ON
   ITD on GCLK3 :	ON
   Open Collector :	AUTO
   JTAG mode :		AUTO
   TDI Pullup :		OFF
   TMS Pullup :		OFF

ATF15xx Verilog/VHDL using Quartus 13.0 SP1

ATF15xx Verilog/VHDL using Quartus 13.0 SP1

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