It's a fine idea to implement your glue logic with a CPLD, but it's also a fine idea to use GALs. Don't let one opinion give you the idea that there's only way to do things, or that there's a consensus among members as to which approach to pick.
I'm not opining there is only one way. My latest POC unit highlights that, as it's all discrete logic.
That said, there is a potential problem with the way he's doing things right now, in that there can be a race between GALs due to differences in internal prop time. GAL prop times are specified on worst-case pin-to-pin values. No minimum is specified and that's where one can run into trouble with two GALs making logic decisions "in parallel." While I'm not saying that is what is happening in his system, the possibility does exist.
Back in the days (around 1991) when I was writing code for a 65C02 terminal server that used two GALs, every so often the unit given to me for testing would go whack-a-doodle for no apparent reason. I spent a lot of time poring over my code trying to find the error that surely had to be causing all the trouble.
The cause turned out to be a difference in GAL speeds resulting in some logic going "backwards." Ø2 was 8 MHz in this unit, which was clipping right along for a 65C02-based system in those days. Timing was somewhat touchy. When the board was hooked up to a logic analyzer it was seen that one of the GALs was slowing down more than the other as its temperature rose (back then, GALS were more power-hungry than now). The board had to be redesigned because of this behavior and the new design ended up with a small CPLD so all logic could be encapsulated in a single device.
morale of the story, throw everything you can into a single chip.
ok nice, sadly quite expensive but whatever, it will work.
i found the same on Mouser as well so i can order it with my other components. problem is that they are out of stock, and it will take a few months for new ones to arrive (acording to the site).
ok now a few questions about somne of the pins on the ATF1504.
I know the use of the 4 JTAG pins, and will avoid using them for IO stuff. (I assume my JTAG connector is correct as i cannot find a pinout of the Atmel Programmer's connector online)
I have an idea what some other pins do, like the GCLR (Global Clear) which probably resets all internal flip flops.
and the GCLK (Global Clock) pins, which are likely used for the clock input of the flipflops, why there are 3 of them though, no idea.
but now the confusing pins:
OE (Output enable), there are 2 of these and one of them is on the same pin as a Global clock, no idea what they are for.
PD (???), there are also 2 of these, again no idea what they might be for.
