BigEd wrote:
It's all true - but note that it's the max cycle time which is the constraint here. The general advice is to go no slower than 100kHz for reliable operation. In practice you've probably got some tens of milliseconds before charge leakage starts to flip values, maybe more: for manual experimentation this is no big deal, but reliable operation in the field is another matter. And if you're trying to debug something, you don't want an extra source of uncertainty!
Off at a slight tangent, but once upon a time a company I was working at wanted to characterise some of the memory SIMs (and other shaped modules) they were making[1] so we built a test rig for DRAM that did all the refresh in software (From a transputer). I recall some of them being very reliable in the small number of seconds range but typically if you didn't refresh them at least once a second then you'd be in trouble.
-Gordon
[1] There was a shortage of 32-pin SIM modules in the early 90's so this company made their own - even sold them for a while too
_________________
--
Gordon Henderson.
See my
Ruby 6502 and 65816 SBC projects here:
https://projects.drogon.net/ruby/
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