I'm trying to understand why RAM has not kept up with Moore's law.

The 6510 has slower clock speed because the VIC was using the other 1 MHz of the RAM?

But today DRAM has ~1GHz but row updates take like 300+ cycles, so how can one compare the figures of the C64 to a modern machine in terms of memory speed/latency?!

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MOS

Interesting question. My guess would have been two things:
- the chips are huge; capacity increase is more important than latency decrease
- caches are huge; spill and fill of cache lines is the important measure
- DRAM cells are getting smaller so the readout of a very tiny charge over a long distance is not getting easier

But then I found this paper, which notes:


So, it might be that a 1Mbit DRAM in today's technology would be very fast, but not worth making.

There's often a lot of memory on-chip these days, but AFAICT it's almost always SRAM, for speed and also because DRAM needs a different process compared to logic. But see
https://en.wikipedia.org/wiki/EDRAM
for in-module memory, which can be DRAM as it's a different chip.

The other points that are well worth noting about DRAM:

For random access, you have to supply a row address, and a column address (because of the way the cells are laid out). One after the other. Faster DRAM is not actually faster for random access. But instead, the more complex modern chips read an entire row of data, so the system (CPU day) can read sequential memory locations at the bus speed, not the slower DRAM random access speed.
The second point is that DRAM chips and EPROM/EEPROM/flash memory are actually analogue internally. When a memory cell is read, an amplifier reads the voltage from the cell and sends the buffered voltage to a comparator. It’s the comparator that decides if it’s a one or a zero. It takes time for this to happen.

Mark

(Page mode access, which is to say in-row access, has been around for a long while - Acorn's Electron used to get the maximum bandwidth from just four single-bit-wide DRAM chips, and their later ARM chip used it to speed up sequential accesses for a fairly major performance boost....
)

Yep, page mode is not new.

And wider data buses (hence more parallelism) allows many bytes to be accessed simultaneously.

Not using external refresh, but instead using on chip refresh circuitry also helps (again, not new).

A lot of other tricks are used to increase the throughput. All of which helps to overcome the inherent slow speed of the DRAM.

Mark

BTW, you can get pretty fast SRAM: 10ns for sure and maybe 7ns. But at those speeds, the delay getting on and off chip can be significant, as can the delay of any glue logic, and the layout of the PCB becomes critical.

Moore's law has given us faster and small transistors, but it hasn't changed the speed of light. It's rather difficult to design at speeds over say 100MHz - although one can casually buy a computer system with 3GHz CPU, that doesn't mean 3GHz is easy. Indeed, DDR4 "only" goes up to 1600MHz, and in the past, IIRC, it's been the case that hanging more DIMMs off one bus causes the bus to be run at lower speeds.

AFAIK it's quite possible, with care, for a hobbyist to design an FPGA system at say 100MHz, which is plenty fast enough for most purposes and still very impressive compared even to 4MHz back in the day. For our kinds of 8 bit systems, the FPGA may even have enough RAM on chip not to need external RAM.

The key point is latency. To get data out of a DRAM cell, the tiny charge on a capacitor has to be carefully guided onto a long wire leading to a very sensitive amplifier, which necessarily has a finite gain-bandwidth product. As process geometries get smaller and more bits can be packed into each chip, the amplifiers get better, but the capacitors also get smaller and so the extra sensitivity of the amplifier is absorbed by that change. This process takes place on the /RAS strobe; there's an entire row's worth of charge amplifiers which act in concert and read a large number of bits into a row buffer. The /CAS strobe indexes into that buffer, and is generally a lot faster and easier in the chip's internals.

In the kind of DRAM chips you would use in an 8-bit machine, it was common to simplify the DRAM handling logic by consistently performing both a /RAS and /CAS strobe for each access. This was even more true where display scanout was interleaved with CPU accesses, so sequential RAM accesses generally had nothing to do with each other even if the CPU was sequentially fetching instruction bytes. So the speed of the RAM was basically defined by the /RAS cycle time, which included not only reading a row of cells and indexing one column of them, but writing the row back to the cells and precharging the wires for the next access.

These days DRAM chips have some very sophisticated interface logic which can queue up several different DRAM row accesses in different banks of row buffers, and also several different column burst accesses designed to fill entire cachelines in a modern CPU at high speed. The CPU itself has sophisticated logic to predict near-future access patterns and load parts of their multi-megabyte caches in advance of need. This means that while RAM latency is still important, the bandwidth of the DRAM bus makes a good substitute for it.

But I recently upgraded one machine with a pair of 64-bit wide, 3466MHz transfer rate, 18-cycle RAS and CAS latency DDR4 DIMMs, which have an effective RAS cycle of just over 10 nanoseconds - somewhat faster than the 200ns RAS cycle you'd pay good money for in the early to mid 1980s. A 20x speedup over 35-40 years is not a rapid improvement compared to logic speed increases, but it's not to be sniffed at either.

Logic speed isn't getting much faster. In fact the change from 7nm to 5nm is expected to slow things down without some improvements in how the transistor are made. Interconnect wiring is getting worse with the smaller geometries as well. Most all of the IPC improvements have been from architecture improvement ( some of which have opened up security issues ). DRAM's speed is being optimized for things like ROW access by separating individual sequential row element to have their own sense amps. This way it can steam the data faster once the first element it read. The processor can then stick it all in cache for maximum speed.
For logic circuits, to get them to run much more that 5 GHz is not practical.
It is quite remarkable that they've been able to do as well as they have. Intel tried to squeeze their 10nm parts to a tighter limits and ended up making a less reliable yield. I expect they were hoping they'd get more improvement over time on their process that didn't pan out.
DRAM uses different parameters than processors for things like leakage. Processors that have transistors that are right on the edge of leakage are faster parts. DRAM parts that are on the edge of leakage are throw away.
Still smaller dimension size means more circuits in a small space. More efficient pipeline and better prediction of speculative execution are where the speed of IPC is coming from. It is not so much from smaller geometries.
Moore's law is really dead. They will run out of tricks soon.
Dwight

Gonna be a real interesting decade when they finally do.