I have a small number of WDC 65C02s to test compatibility with normal 6502s, etc. Basically, I wanted to see if the WDC chips work. In any case, I simply can't get the processors from WDC to run. I have built 6800, 6809, 68000, 6502, Z80 SBCs, but no matter how simple I make the WDC 65C02 board it just won't work. I have a 5 chip computer, the WDC 65C02 at 2 mhz, a WDC 65C22 VIA, a 32K 120ns SRAM, 32K 150 ns Eprom, and a GAL22V10B for glue, the design is simple, simulates fine. My simple question is:
"Is there any voodoo problems with the WDC chips that are NOT in their docs?"
I have built 2 systems wire wrap based, and both exhibit the same "loop" when they power up, the abus seems to be changing (I don't have a logic analyzer, so I can't see the exact addresses), but I vector to the ROM and the upper address lines should all be high, there are not, they are toggling, it's all very weird. The system is out of reset, all the pins are pulled high, low, whatever they need, I see activity on the R/W line, but its like the processor is not trying to execute code, but doing some kind of state loop --
-- Pixel
WDC 65C02 trouble
What are you using to see these logic levels?
You could try Lee Davison's NOP generator to test things. It hard-codes a NOP onto the data bus. The cpu resets, goes to the reset vector, jumps to address $EAEA and starts execution. It the see's NOP on the databus and executes them. The address lines should all cycle (from $0000 to $FFFF and repeat). The A0 will be at the fastest speed, and then each higher address is divided by 2. The data bus should be solid with EA. The R/W should be high (all read commands).
Also, be sure the NMI & IRQ are held high.
If your program is staying in ROM, is it writting any data to RAM (don't forget stack usage such as JSR/RTS)? If not, the R/W should stay high.
Also, the BE & RDY lines should be held high.
Good luck!
Daryl
You could try Lee Davison's NOP generator to test things. It hard-codes a NOP onto the data bus. The cpu resets, goes to the reset vector, jumps to address $EAEA and starts execution. It the see's NOP on the databus and executes them. The address lines should all cycle (from $0000 to $FFFF and repeat). The A0 will be at the fastest speed, and then each higher address is divided by 2. The data bus should be solid with EA. The R/W should be high (all read commands).
Also, be sure the NMI & IRQ are held high.
If your program is staying in ROM, is it writting any data to RAM (don't forget stack usage such as JSR/RTS)? If not, the R/W should stay high.
Also, the BE & RDY lines should be held high.
Good luck!
Daryl
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