Yes I know exactly where it is. When I found the short after I soldered the VRegs, I went to the 2nd unpopulated board and witnessed the same thing. Then I knew I had a problem and started searching the design for vias that were incorrectly assigned to a layer. But then I found it and it was a strange mix of relief and disappointment. Relief that the manufacturing process was solid, disappointed I did something so stupid and so close to the end of sending the design in for fabrication. I just checked my logs, the design was sent in 3.5.2019. I checked the design entry to my backup file 2 days earlier @ 3.3.2019. No problem there.

What really pisses me off is I failed to mention the modification in my changelog!

You can see here where the problem is circled in yellow to the left of micro-SD silkscreen, I don't think there's anything I can do to fix it.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

March 20 2019 was the last update. I've had other projects (speakers, engine) because I have sort of gave up on this one... The single most important reason was the unavailability of the 3.3V SyncRAMs and the fact that I've made a fatal mistake in the multiple voltage levels the FPGA had to deal with. Recently I've found 4Mx18 RAMs @3.3V @250MHz and purchased 4 of them. This project is still alive...
Yes, 4Mx18! This project was originally spec'd for 2Mx18, which is enough to hold 1 video frame of 1080p.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

The heart of this project was a Silicon Labs I2C programmable 'can' oscillator Si570. The CMOS version was spec'd @ 10-160MHz. This was exciting because it's not just your boring single frequency oscillator and it should be good enough for video.
Now I plan on incorporating a newer device Si514, with a programmable frequency range from 100kHz to 212MHz. While the Spartan 6 FPGA does have very powerful clock generation, for the most part, the multipliers/dividers need to be programmed on startup. The Silicon Labs device is on the fly programmable and what an awesome range. I should be able to software set any VGA video standard up to 1900x1200 without having to reprogram the Spartan 6.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I think at this point, it's a good idea to start a new topic and let this one die. Parts suppliers have changed, larger RAMs have been added, SPDIF has been added.

There are multiple goals possible from a barely populated board to a fully populated board... Of course, there will always be either an ultra fast 6502 softcore or a slightly slower 16-bit 65org16, based on Arlet Ottens 6502, inside the FPGAs I use.

I shall post when I order the next run of boards which should be before EOY, hopefully next week.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I ordered the boards. Be patient with this old geezer. I'm writing up a whitepaper on the new board. I tried last night to start a new topic but over an hours worth of typing online resulted in some kind of login timeout and lost all my work. Patience is definitely required in this hobby of ours.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Aargh, it's horrible when you lose a long draft! Best perhaps to compose somewhere else, or to post early on and then commit a series of edits. So long as you mark it as a work-in-progress that shouldn't cause any confusion.

On the plus side, sometimes when you lose your work and have to re-do it, it comes out quite easily and even better!

Looking forward to reading it!

I'm sorry, I should have put a link to redirect to the new thread. Here it is.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Phew! I finally made it to the end of this thread! But, oh dear, now there's another one. :-)


Actually, on this board at least, if you simply preview every ten or fifteen minutes I think that will avoid timeouts that lose your text.

But for any serious writing I'm doing for posts, I have a separate file in a private Git repo where I do my typing-up. (The Git repo for backup and so I can move from machine to machine while working on draught posts.)

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Curt J. Sampson - github.com/0cjs

Yes, sorry. I don't like mega threads myself. I'm trying my hardest to not do this for the A/V board.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Maybe you should do a youtube video about it... I mean a video made by the actual guy making the board would be alot more interesting than these other 8-bit wannabee-videos there (no offense).

Yes I plan on videos once the new board (in the new thread) is at least semi-functional. Cell phone video quality has come a long way in the last 6 years. Back to work...!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502