Interesting findings in the team6502 trove

[BigEd]

Nearby, Jen Winograd shared a link to a new documentation collection effort on the web at team6502.org, starting with the papers belonging to her father and progressing to recollections and collections from other original workers in the 6502 team.

I thought it would be handy to have a separate thread for noting interesting things that we find there, and discussing them.

The website availability is a bit intermittent, perhaps due to great interest. Please don't clutter this thread with reports of difficulty!

[BigEd]

Some noteworthy findings in documents:

From "mos_brochure" (Q3 1975?)
- offering calculator chips (single chip scientific!), ROMs, microprocessors
- also 7 kinds of 'custom arrays' - avionics, games, automotive, vending machine, logic control, coin changers, electronic organs.
- did $17.5 million of business in year to Feb 75
- plant is from 1970 and has 60k square feet
- production is on 3 inch wafers at a rate of 500k to 750k finished "arrays" per month (perhaps meaning raw die, rather than finished wafers, or good die.)
- earlier chips in P channel metal gate, then P channel with depletion, and micro products in N channel with depletion. (I believe MOS were a very early adopter of Ion Implantation and depletion devices.)
- Synertek is a second source, established supplier of RAMs built in N-channel process
- 6502 beats other offerings in all but one of a collection of third party benchmarks
- no exact 6800 compatibility because they want "significantly greater addressing flexibility"
- primary objective to be low cost
- second index register more than compensates for loss of second accumulator
- 8 bit stack pointer helped to reduce the cost of the chip and should be more than adequate
- will deliver several thousand parts during September 1975. Delivery in volume for Q4.
- some quotes:

Quote:

With the introduction of a $20 microprocessor MOS Technology Inc once more set a new pattern of cost effectiveness for the industry. And we plan to maintain this leadership in the microprocessor area in the future exactly as we have done with calculators in the past.

Quote:

MOS Technology has been sampling selected accounts since July 1, 1975, with the result that the microprocessor and our cross assembler are currently running in several of our customers' houses.

Quote:

Current plans [for software support] involve having the software available on several of the more popular Time Sharing services. In addition it will be available for deck sales. Batch decks for the CDC, IBM, and PDP-11 class machines are available and we will support several other popular mini and major computer systems in the near future.

From "chuck_peddle_letter_to_customers_feb_1976"
- 2MHz parts now available
- Correction to single instruction/single cycle schematic (mentioned, not shown)


From "the_mos_catalogue_pinned_to_april_1976_letter_to_customers":

- 6501 is no longer mentioned
- the 6502 "programming model" diagram has dotted lines to indicate "forthcoming members of family" which extend registers and stack pointer to 16 bits and add 16 bits of I/O registers. Likewise the unused bit in the status register is labelled "forthcoming feature".
- RDY input and pipelined architecture mentioned, but not the SO input
- "True indexing capability" (presumably better than 6800s?)
- a symbolic cross-assembler for various time-sharing services and also available for purchase
- a software emulator for "determining the viability of operation and calculating the timing of sections of code" - for batch or interactive use
- The TIM (monitor ROM in RRIOT) and the KIM-1 single board computer are mentioned
- The PIA, VIA, ROM and RAM all offered by MOS. RAM is 1kbit, ROM is 2kbyte

In "april_1976_letter_to_customers" we see
- MOS and Moto have settled their suit and cross-licensed relevant patents, and the 6501 is withdrawn
- 9 micros, from 6502 to 6515
- the 6512, 13, 14 and 15 are variants with two-phase clock inputs, to support the timing needs of multiprocessor systems
- three new peripherals to be introduced: 6520 PIA (designed by Synertek), 6522 (VIA), 6532 (RIOT)

[BigEd]

Also interesting:

- Rod Orgill named the SO pin after his beloved rescue dog, Sam Orgill.

- John Paivinen co-founded MOS Technology in 1969 with $3.5 million of capital from Allen-Bradley.
- First part produced just 12 weeks after equipment installation

- Sydney-Ann Holt acted as a go-between in between the 8 ex-Moto people (The Motorola Eight) who joined to make the 6502 and the existing MOS Technology staff. She also has some interesting commentary on being a woman in engineering at that time. And a story about a man with damp socks erasing some of the artwork on the mylar, during checking.

[cjs]

BigEd wrote:

- "True indexing capability" (presumably better than 6800s?)

I've been wondering about this for a while. Perhaps they mean that you can use an index register as the index into an array (up to 256 bytes long, obviously) that starts at any location in memory?

On the 6800 you couldn't do this because the only indexed addressing mode held the base in X and took the index from a byte immediately following the instruction, e.g.,

Code: Select all

    LDX ptr
    CLR 0,X
    CLR 1,X
    CLR 2,X
    ...

Thus, when accessing an element via indexed mode you need to know the offset at compile time:

Code: Select all

    LDX #ptr    ; 3 cycles
    LDA 17,X    ; 6 cycles

Reasonable enough if you're accessing fields within a struct, but I don't know what you do if you have an index in a register and want that offset from a base address. Best I can think of is:

Code: Select all

    ;   B contains the index into ptr
    LDA A ptr
    ABA         ; add B to A
    STA A temp
    LDA A ptr+1
    ADC A #0
    STA A temp+1
    LDX temp
    LDA A ,X

Kinda ouch!

And of course even just iterating through an array, you needed to keep the count in another register as well (though of course you had an "extra" register for that):

Code: Select all

        LDX ptr
        LDA B 17  ; count
loop:   CLR ,X      ; 7 cycles
        DEX         ; 4 cycles
        DEC B       ; 2 cycles
        BNE loop

Still, especially looking at the cycle counts, it gives a bit of insight into how the 6502's design is not as dumb as it might seem at first glance (or to me when I was young, in particular).