I found the datasheet (here:
http://web.archive.org/web/%2A/http://highgate.comm.sfu.ca/~rcini/classiccmp/pdf/ds_6500.pdf
- see page 8 or the snippet below)
Sounds like pulling \RES to 10v overrides all memory reads directing them to port C. So you feed opcodes and operands into port C as if it was a 6502 data bus. (At minimum you'd need something like an EEPROM with a counter driving the address pins.) But those instructions can't read ROM because all reads are redirected. Why can't you just bring \RES down to 5v for the cycles where the ROM is read?
Perhaps you can, but if you're aiming to test the chip, you'd learn more if the code running from port C writes a secondary program into the 64 bytes of page 0 RAM. To run that program, it must be possible to feed in a JMP #0000 to port C and then bring \RES back to 5v in time for the next access.
Code:
TEST LOGIC
Special test logic provides a method for thoroughly
testing the 6500/1. Applying a +10V signal to the \RES line
places the 6500/1 in the test mode. While in this mode, all
memory fetches are made from Port PC. External test
equipment can use this feature to test internal CPU logic
and I/O. A program can be loaded into RAM allowing the
contents of the instruction ROM to be dumped to any port
for external verification.
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) Unfortunately, I don't know the hex opcode for this instruction.
