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PostPosted: Mon Apr 15, 2019 2:53 am 
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Joined: Tue May 05, 2009 2:49 pm
Posts: 113
(copied from cbm-hackers mailing list)

Hi!

Some time ago I received Jim Brain's Fake6509 for testing. If you
followed the last year's thread, it worked perfectly with original 6502
and various other versions (including the 65C816) to emulate the 6509
for CBM-II, but when used with Rockwell's R65C02, the computer
mysteriously failed the memory test.

So here are tests done with a logic analyzer for:

(a) Original 6509 CPU
(b) Fake6509 with 65C816
(c) Fake6509 with R65C02

https://drive.google.com/drive/folders/ ... Y1dU4DGxfF

What you see there is the CPU executing a STA ($93), Y instruction at
$FFABA, whis is a part of KERNAL's memory test. It is about to write $55
to $10002, which will then be read back to see if there is RAM at this
address.

Both the 6509 and the 65C816 execute the instruction in the same way.
But if you look at what the R65C02 is doing, the value $0094 is kept at
the address bus one cycle longer, and the destination address $0002
appears there for only one cycle, as opposed to two cycles for the 6509.
This is too late for the CBM-II maiboard to latch the address for the
DRAM, so the value gets written to $10094 instead of $10002, and the
memory test obviously fails.

Regards,
Michau.


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PostPosted: Mon Apr 15, 2019 2:53 am 
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Joined: Tue May 05, 2009 2:49 pm
Posts: 113
I have updated the github repository with the v4 code here: https://github.com/go4retro/Fake6509. I see a few straggling GPL v3 notices I need to fix, but as previously noted, the project and files are released under the MIT license.

A few notes:

  • As Michal shows, the PCB and CPLD support the NMOS 6502, CMOS 65C02S, and 65C816S in emulation mode
  • I have also added support for the 65C816S in native mode, in which the bank register is driven directly by the 'C816. Placing the CPU into native mode will also switch into this mode, which means care must be practiced to set up the '816 bank to match the current 6509 'Execution Bank' before switching into this mode. Location $0 and $1 will still be visible while in native mode in the current HDL.
  • The upper 4 bits of the bank registers can be enabled for all 6502 variants and for both emulation and native mode for the 'C816 by sending $55,$aa,$00,$01 to $0001. In this mode, the upper 4 bits of the bank register are present at 4 pads on the PCB and will be returned during reads of the specific register. The upper 4 bits will follw the lower 4 bits concerning usage (i.e., in native 'C816 mode, they represent the upper 4 bits of the '816 bank register). Use of the upper 4 bits in practice is left as an exercise by the CBM-II owner.
For those interested, I will determine pricing and place a pre-order on my site in a few days (I need to get a quote from the assembly house).

Jim


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PostPosted: Sun May 05, 2019 5:31 pm 
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Joined: Wed Mar 02, 2016 12:00 pm
Posts: 343
Is it possible to use this to plug a 65816 into my B610? Would it boot?


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PostPosted: Sun May 05, 2019 7:42 pm 
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Joined: Tue May 05, 2009 2:49 pm
Posts: 113
It would and it does.

Jim


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PostPosted: Tue May 07, 2019 5:15 am 
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Joined: Wed Mar 02, 2016 12:00 pm
Posts: 343
brain wrote:
It would and it does.

Jim


Oh, great! I need to get one then! Would be really interesting to run 65816 code on it.


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