Clock circuit problems

kc5tja · Post by **kc5tja** » Mon Jul 23, 2007 4:31 pm

I researched this, and it looks like F-series logic is capable of managing the slew rates, if only barely (74F00 had a slew of precisely 5ns -- right on the verge of what WDC's parts wanted). I ended up using a pre-packaged oscillator module, however, because it was cheaper.

I'm sure it also depends on the construction method as well. PCBs might have wildly different slew characteristics than wirewrapped or breadboarded circuits.

RyanS · Post by **RyanS** » Tue Jul 24, 2007 4:59 pm

I'm using a Rockwell chip, which has a maximum slew of 10ns. The datasheet for the 7404 that I'm using says the typical low-to-high switching time is 12ns, but when I tried it out, it seemed to work.

fachat · Post by **fachat** » Tue Jul 24, 2007 5:22 pm

RyanS wrote:

I'm using a Rockwell chip, which has a maximum slew of 10ns. The datasheet for the 7404 that I'm using says the typical low-to-high switching time is 12ns, but when I tried it out, it seemed to work.

I'd think for new designs TTL families like 'ALS would be in order, wouldn't they? Don't know about their switching time, but in general they are much faster (almost as fast as 'F)

André

DonnaD · Post by **DonnaD** » Wed Jul 25, 2007 1:35 am

kc5tja wrote:

The 74LS04 technique may work for chips other than WDC's -- I've found that when WDC says a maximum slew of 5ns is required for the clock, they very much mean it. Even 6ns is enough to produce flakey chip operation in my experience.

Well, I used the 74LS04 with WDC W65C02S and also the W65C22S and it worked fine. Can you point me to information regarding this? I would be interested.

kc5tja · Post by **kc5tja** » Wed Jul 25, 2007 4:28 pm

It's in their data sheets.

I'm going off of my own experience with the W65C816SP-8 processor (14MHz chip), as manufactured some years back (maybe 5 years?). I ordered them back when WDC required a $100 minimum order.

DonnaD · Post by **DonnaD** » Wed Jul 25, 2007 8:00 pm

Your right... the W65C02S datasheet says slew of 5ns, but the 74LS04 is actually 9-10 ns.

I wonder how I could check to see if my system is being affected? It appears to work fine... never crashes... will run for day's on end. hmmm.

Maybe it would only show up in higher frequencies... i'm only running at 2Mhz... maybe I'll order a 4mhz and and 8mhz crystal and see what happens.

GARTHWILSON · Post by **GARTHWILSON** » Wed Jul 25, 2007 9:06 pm

Donna, two things:
1. You're using a 65c02, which has a schmitt-trigger clock input, and you can even hang a resistor and capacitor right on the processor for the clock. For that, even hundreds of nanoseconds' rise time is no problem.
2. Samuel was using the 65816 which has a different clock arrangement, and he also made it on the socket-type breadboards with big hoops of wire arching over the parts. Sometimes it's very convenient and I've done it many times, but it's definitely not the best for making a computer. In that situation, a slow rise time will fall prey to a lot of radiated ringing and other funnybusiness from neighboring wires.

kc5tja · Post by **kc5tja** » Fri Jul 27, 2007 12:02 am

My oscilloscope traces showed relatively little signs of ringing on the clock signal (indeed, other signals showed signs of interference caused BY the clock). I am equally confident that wire-wrapping simply would not have helped this situation either.

Originally, that was what I thought the problem was, and made it a point to straight-line the connection from the clock oscillator to the CPU to the VIA, and to relocate the clock physically adjacent to the CPU itself. This did not help reliability at all.

The only thing that worked was the use of an oscillator module.

It would seem that the 555 timer chip doesn't have the capacity to drive tens of picofarads plus a bit of inductance (each breadboard row of pins contributes about 5 to 10pF of capacitance).

Wally Daniels · Post by **Wally Daniels** » Fri Jul 27, 2007 5:43 pm

Hello Everyone,
This is one area that WDC should spend some time on if for nothing else
but to dispell alot of the myths that are hard to discredit based on the
limited resources most of us hobbyists have. WDC likes to cut and paste
their documentation sometimes so you have to be carefull.
For anyone that is interested in this subject of oscillators especially
those that use logic gates try searching for " Pierce Oscillators" on the net.
Next there are inexpensive alternatives " out there " like Epson's
SG-531 series which is low power and comes in a small plastic package.
Check out DigiKey as a source. I use them with my 65C265 projects
and find they work really well if you want to quickly swap one freq for
another. I think their price is under 4.00
The last point is one which Garth ( Wilson ) and I discussed over the
years. That is the max freq using wire-wrap. I can honestly say that you
can run wire-wrap to at least 8Mhz reliably. I am currently running my
present sbc at 8Mhz using a prototype technique discussed in Circuit
Cellar's December 2000 issue by Stuart Ball. I don't want to start a flame
war here, but don't be scared of wire-wrap.

Hope everyone is enjoying Summer

-Wally

DonnaD wrote:

Your right... the W65C02S datasheet says slew of 5ns, but the 74LS04 is actually 9-10 ns.

I Maybe it would only show up in higher frequencies... i'm only running at 2Mhz... maybe I'll order a 4mhz and and 8mhz crystal and see what happens.

dclxvi · Post by **dclxvi** » Fri Jul 27, 2007 9:59 pm

To anyone interested, there are several threads where kc5tja discusses his issues with the slew rates (and PC parallel ports). Look for Kestrel 1 (or it's original name Kestrel 8k or Kestrel 32k -- before wisely deciding to number the Kestrel by its design, it was named by the amount of RAM it had). You could also look through kc5tja's posts, but he's got one of highest post counts here (second to Garth, I would guess).

Wally Daniels wrote:

Hope everyone is enjoying Summer

And um...to those of you in the Southern Hemisphere, enjoy the winter!

(I couldn't help myself. There's a number of Aussies and Kiwis here, though.)

kc5tja · Post by **kc5tja** » Sun Jul 29, 2007 4:49 pm

Quote:

(I couldn't help myself. There's a number of Aussies and Kiwis here, though.)

Well, everyone knows that there is no hope for you folks -- not only do you drive on the wrong side of the road, you also live in the wrong season. But that's OK -- we like you just the same. ;D

kc5tja · Post by **kc5tja** » Sun Jul 29, 2007 5:02 pm

A well-designed, wire-wrapped circuit ought to be able to handle much, much faster than 8MHz. Remember that many early home computer circuits, particularly video circuits, were engineered so that they perform tasks on both phases of the clock, and operated with an 8MHz to 16MHz clock -- thus, 32MHz ought to be well within the realm of possibility of wirewrapping, depending on your circuit complexity and level of pipelining. The Amiga's AGNUS, Daphnie (later DENISE), and (then) Portia (later, PAULA) boards (yes, boards! See http://www.floodgap.com/retrobits/ckb/s ... raine.html Note that the site gets the order of Portia/Paula backwards.) were all wirewrapped, accepted a dot clock of 28.2828MHz, and had logic which worked at a variety of speeds, ranging from 14.31818MHz to the video serialization and sprite logic, 7.15909MHz to the AGNUS DMA circuits, to 3.579545MHz to the blitter logic (based on its low clock rate, I'm assuming the blitter was implemented as a giant, combinatorial logic ratsnest with minimal pipelining. This design was carried forward into silicon, unfortunately, thus limiting it to drawing only about a million pixels per second, when it could easily have handled 2 million. Oh well.)

But that wasn't the point -- slew rate sensitivity of WDC's parts was.