I've finally rerouted the missing address line despite the holidays and it wasn't as much work as originally thought. I thought I'd have to pretty much reduce ALL the trace to trace distances, but things look good and are in proportion from just snaking 1 line thru and nudging just a few others over...

Maybe some pics are in order? I'm still wresting with the screen capture program that can capture images from a scrolling window. I've used it on other projects here for real nice close-ups of board layouts but I may have to pay for an updated version to work with Win10. When the screen capture finally does cooperate, I'll post pics of all 4 layers to the header.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I've got the SnagIt program working! Pics posted to the header. Just a few pins left to be connected on the videoDAC and I think it's done. Very soon and I'll start the constraints file for the Spartan 6. This will force me to check all FPGA traces/pin assignments.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Wow, I've realized this has been the longest delay I've had after entering a new version of the board layout to the 'library of progression'. Been 6 days...

I've finally decided instead of trying to understand some tricky modes of this videoDAC, that I would just put vias on those 5 pins and 10 vias close by for 1.8V & GND. If they need to be switched signal for any purpose there's the leftover pins from the Slave S6 which have vias as well. They're all purposely large enough to fit wirewrap wire into nicely for soldering.

Lastly tonight, I start the Master S6 constraints file!

Cheers

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Hello! I'm very sorry for the delay. Very busy here with work and other stuff...

Progress report:
Constraints files haven't been completed yet, but I did complete the total BOM. Counting up the cap's and res's was tedious but it is complete. Head post will be updated tonight.

I've been looking at a 48-pin QFP IC I think I will add to give this project abit more excitement, but without routing much of the traces especially since it will fit in the current layout and it's worth the $ IMO. I'll just add vias for the data connections for future soldering manually with wirewrap. I don't want to delay ordering boards any more than necessary. It's a PCM9211. It's basically a dual digital audio ADC with serial data out and SPDIF I/O which is really attractive for some kind of active input this project can process and display.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Ordered the cap's, res's, PCM9211, SPDIF receiver and transmitter.
Placed the PCM9211 and connected the I2C signals on the board layout. Also the 5V filtered necessary for the analog ADC's on the PCM9211.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

What good is an audio ADC without a DAC and some DSP? Especially when then DACs and DSP are on a 48-pin QFP... I'm going to make this work, even if the board needs a little expansion for the connectors.
The idea here is to have an ADC with SPDIF outputting a serial stream to the FPGA through 3 pins. In the beginning developmental stages, the FPGA does nothing except route these 3 pins direct to the ADAU1701. Afterwards, the FPGA can take the ADC data stream and modify it, record it, and/or display the waveforms from memory or in real-time.

Block diag needs serious updating...

Here's where I'm trying to fit the last 2 48-pin QFP's on the board layout, U21 & U22 on the top left.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Been doing more research... I'm going to stop with the PCM9211 addition. I'll try to keep the footprint of U22, the ADAU1701. I'm not fully grasping how to connect it to the PC in order to use the free Sigma Studio software to program it. I think I saw something like a USB to I2C adapter, but I don't have time for that right now.

I'm starting to get an itchy trigger finger to manufacture these boards.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

The PCM9211 requires a 24.576MHz crystal for the 24bit 216kHz ADC's. 216kHz is sorta non-standard, I'll be using 192kHz. Anyway, using the Xilinx Clocking Wizard within the Core Generator tool with 148.5MHz input as the main clock, the S6 can generate a 24.579 Mhz so no need for the crystal and 3 other components. I love this tool because it's so quick and easy: (148.5MHz/5)x24)/29. So, I was able to snake through the clock signal from the FPGA in the layout.

If the resolution is changed, I would have to try to make the pixel clock frequency a derivative of 148.5Mhz for the audio to work. Else I would have to program the CMOS oscillator itself for the exact pixel clock frequency and the PCM9211 would be non functional.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

And here I am, naively thinking up just how many things I can drive from a single 24MHz master oscillator with integer divisions only…

Hello, been reading more up on the PCM9211. It turns out the ADC's run a max of 96kHz x 256 = 24.576MHz, which is fine. I think the 216kHz spec comes from a direct routing from optical in to optical out, like in a pass-thru situation. Only thing left to wire is the optical output and input. I have the optical modules I chose in the updated parts list. I already have 99% of the parts, just a few odds and ends for this PCM9211...

U22, the ADAU1701 had to be removed in order to make room for the optical receiver and transmitter modules. They will go opposite the SD Card slot, on the backside of the board.

Getting very close now.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I believe I'm 99% complete, with the remaining 1% to update the head post. I've add some LED's to show when there is an error and when there's no PCM detection from the PCM9211. Everything there is fully wired in now for TOSLINK In and TOSLINK pass-thru.

I am ordering boards abit prematurely, without writing the FPGA constraints file. I figured there will always be something that needs to be corrected after the first run of a new project board. I'm 100% the VDD & GNDs are correct on the SyncRAM's. These are the most expensive, so if something is not wired correctly, I'll be able to un-mount and reuse them on another board run.

Tomorrow I order them.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Updated head post with 1st production board layer pics. Was able to get 2 Type: 4 Layer - 5 Day ProtoPlus Silver (RoHS) Service boards for $155 including shipping

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Nice one - the moment of truth approaches!

Yes! I have rolled the dice. Another board, this one took 2 months longer than my previous ones... BTW there were 573 vias. Luckily with the service I chose there was no penalty for so many.
Also, I'm going to be kind to myself. Since I already found a minor mistake (the silkscreen for S2 is in the wrong spot), anytime I save an updated version of the board I will be including a text file describing all changes.

First order of business after they arrive is to test the powers/ground connections for shorts.
Next is to solder in the voltage regulators and associated cap's/res's, ,measure them and check them out on the scope. Since I'll be using a switching PC power supply for the main 5V in, I'll be looking at the baseline noise there for each regulator. Probably not much to look at, but better safe than sorry.
If I make it that far, I'll solder in the JTAG connector, Master S6, SPI Flash and components and see if ISE14.7 can program the S6 by way of the Flash. I'll be using my trusty HS1 USB-TJAG Programming cable. This is where I worry my design might start to choke. If not here, almost definitely with the Slave S6 in JTAG series.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502