Cooling reduces resistance but doesn't change capacitance
much.
Still running a processor at liquid nitrogen temperatures can
significantly speed a processor.
Dwight

Hi All,

I'm planning to use 25cm of standard IDC cable for a bus structure that will be driven by AC logic. I also plan to use AC parallel termination.

Given the following data for IDC:
Impedance - 100 ohms
Propagation delay - 4.53 nS/M

And using the rule of thumb that the RC time constant for parallel termination should be at least 3 times the line delay:

Line delay = 4.53/4 = 1.13

-> RC > 3.9 nS

So if R=100 ohms then C > 3.9 pF

Does this sound about right?

_________________
Bill

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Doh! So much for my degree in math.

Thanks Garth. Yes I plan to ground every 2nd line in the cable.

We’re you ever able to look into why I’m not receiving any notifications?

_________________
Bill

I mentioned this to Mike and then forgot. My apologies. I'll get back on it. Make sure your email service is not treating it as spam. (Maybe you already mentioned that.) We had a similar problem on AnyCPU.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Just checked Garth. There is nothing on hotmail that seems to be set to stop it. But then again, it's hotmail - they do whatever they like to do.

I'll change to another email address not administered by the evil empire and see if that works b better.

_________________
Bill

Here is a nice document from TI on high speed layout considerations. Not sure if it had been linked to before...

http://www.ti.com/lit/an/scaa082a/scaa082a.pdf

In any case, I have a question for those more seasoned in this stuff.

Id you have a typical 4 layer board:

Signal
GND
Vcc
Signal

Is there a preferred reference plane (GND or Vcc) to run traces over, if you have a choice? In other words, for the layout above, is better to run traces om the top (closest to GND) or on the bottom (closest to Vcc) or does it not matter?

Oh, also ... I was talking with a guy I know recently about me little 14mHz 6502 project. He recommended two things to me. 1) make the board larger than required in order to have a wide margin around the circuitry to reduce impedance in the GND and Vcc planes. and 2) Use copper pours on both the top and bottom to further reduce impedance on the power supplies providing these copper pours completely enclose the circuitry by a wide margin (see attached image).

What do y'all think of these suggestions?

_________________
Bill

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks Garth,

The board is the size it is for the convenience of fitting into the casing, so that's not an issue in this case. Thanks for the tip though.

I followed your process advice on changing traces and eliminating vias. I was able to shorten the over-all trace length by about 30cm and reduce the vias from 74 to 33. I spent another 10 hours pouring over it and was not able to see a way to eliminate one more via, so I guess 33 is it.

To even eliminate the 41 I did took some rather unusual pains (at least for me) to accomplish. They included tossing out a 74373 in favor of a 74573, using 74245s instead of 74244s (you can define their direction without flipping them around), redefining the pinout of the GAL and taking advantage of the fact the order of address and data lines going to RAM and passing through buffers and data registers is immaterial (not so with I/O devices and ROM - for obvious reasons).

It is unfortunate that the 6502 pin-out is so at odds with the pin-out of memory chips. That is the single largest contributor to the via count.

After reading some published info on copper pours, I have decided to pass on these. They can certainly cause more trouble than they solve in digital circuitry.

_________________
Bill

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

This is a significant point, and needs to be repeated early and as often as necessary.


viewtopic.php?f=7&t=342

Mike B.

Trouble with that is that is that most SRAMs and EEPROMs use very similar pinouts(In DIP, at least, and mine use exactly the same pinouts), meaning that it simplifies the routing to put them right next to each other on the PCB.
If I did do that with the RAM lines, I would probably end up putting the ROM near the CPU, on the other side from the rest of the ICs, and do the routing just that part.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Yes, I am aware of that. You'll even find it in my last post. But to DTR's post, it can sometimes be of limited use, unless you want to scramble your ROM too. In my case I was using it as an intermediary step that saved me a couple of vias and some trace length as I had the RAM between the ROM and the CPU, but I've since found it more advantageous to place the Rom between the RAM and the CPU. Still my best measures were substituting 7457Xs for 7437Xs and 74245s for 74244s. As well, using GALs as glue logic is a huge benefit as you can redefine the pin out as desired to improve routing.

_________________
Bill

Here is a good video on this subject:

https://www.youtube.com/watch?v=STCGzanAyR0

Gets into a lot of detail we may not need in the 6502 world, but better stuff to have in your brain than the latest episode of The Gilmore Girls. Is that still a thing? I remember getting kicked out of the TV room so my better half and our daughter could watch that show.

_________________
Bill