Daryl
Turnkey get-started-fast solution
faybs wrote:
One thing we could use is the DLP-USB245M. It's a small module that takes parallel 8 bit data and outputs it from a USB peripheral port; from Windows or Linux it just looks like a serial port. It's not too cheap ($25 from mouser.com) but it seems to meet a lot of the criteria people have been discussing.
Daryl
Well spotted, I didn't notice that one. Looking at the datasheets, it looks like the 245R is cheaper than the 245M because the R has more components built into the chip, other than that they seem about equally capable. One thing I don't like about the R compared to the M is that the R's pinout is likely to make a single sided PCB a bit messy (the M has D0-D7 all neatly next to one another while the R has them all over the place and not in order). If the plan is to have a dual sided PCB, then it's not as big a deal.
faybs wrote:
I was thinking that a neat way to make this sbc simple yet versatile would be to make it behave like a BBS - all communication with it is over a single serial port (RS232 or USB). User interfacing can be done using ansi/vt100 escape sequences (if it's good enough for emacs it should be good enough for anything we may need)
I've been working on some thoughts....
We use a 65C02 with jumper options for a 65C816. We use a TTL OSC for the clock (the user can choose their own desired frequency) and a reset switch (or reset device like the DS1813, etc). Add a pull-up resistor SIP pack for the NMI, IRQ, RESET, BE, etc.
We use three 28 pin DIP sockets for the memory. One could be jumper-enable to support 27256 EPROM or 28356 EEPROM. The other two would be for SRAM0 & SRAM1 (optional). We could also add pads for a .3" wide DIP for the Cypress SRAMS.
If we choose to use the GAL 16V8 for the decoder, here is how I was thinking of using it:

The CLK2 and R/W would be used to decode /MRD & /MWR outputs such that either would only be active during the CLK2 logic high state.
The Address inputs will select RAM0 when A15 is low.
RAM1 or ROM will be selected when A15 is high, based upon the switch input. In either case, RAM1 is written when A15 is high.
The /VIASEL line can be placed anywhere is the address space that we desire... $FExx, $80xx, $7F00, $02xx, etc. The associated RAM or ROM would be deselected for that page. We connect /VIASEL to the /CS2 input on all VIA's and then put A4 in VIA1 CS1, A5 on VIA2 CS1, and A6 on VIA3 CS1.
A7 can either be used for a 4th device, expansion port, or we can decrease the IO space to 128 bytes.
Finally, we provide connectors for the IO pins on VIA1 & VIA2. For VIA3, we place them such that a daughter board could be attached to handle the desired Human Interface.
I suggest using standard pin header pads on the board and using the 90 degree pin headers and using standard ribbon cable to tie the boards together. This should prove less expensive than the stackable connectors. You could also provide pads on the top & bottom edge of the board and split a pin header between the board.
Has anyone tried this?

Any comments?
Daryl
We use a 65C02 with jumper options for a 65C816. We use a TTL OSC for the clock (the user can choose their own desired frequency) and a reset switch (or reset device like the DS1813, etc). Add a pull-up resistor SIP pack for the NMI, IRQ, RESET, BE, etc.
We use three 28 pin DIP sockets for the memory. One could be jumper-enable to support 27256 EPROM or 28356 EEPROM. The other two would be for SRAM0 & SRAM1 (optional). We could also add pads for a .3" wide DIP for the Cypress SRAMS.
If we choose to use the GAL 16V8 for the decoder, here is how I was thinking of using it:

The CLK2 and R/W would be used to decode /MRD & /MWR outputs such that either would only be active during the CLK2 logic high state.
The Address inputs will select RAM0 when A15 is low.
RAM1 or ROM will be selected when A15 is high, based upon the switch input. In either case, RAM1 is written when A15 is high.
The /VIASEL line can be placed anywhere is the address space that we desire... $FExx, $80xx, $7F00, $02xx, etc. The associated RAM or ROM would be deselected for that page. We connect /VIASEL to the /CS2 input on all VIA's and then put A4 in VIA1 CS1, A5 on VIA2 CS1, and A6 on VIA3 CS1.
A7 can either be used for a 4th device, expansion port, or we can decrease the IO space to 128 bytes.
Finally, we provide connectors for the IO pins on VIA1 & VIA2. For VIA3, we place them such that a daughter board could be attached to handle the desired Human Interface.
I suggest using standard pin header pads on the board and using the 90 degree pin headers and using standard ribbon cable to tie the boards together. This should prove less expensive than the stackable connectors. You could also provide pads on the top & bottom edge of the board and split a pin header between the board.
Has anyone tried this?

Any comments?
Daryl
Most printed circuit boards are substantially thinner than the 100 mil spacing between IDC connector pins. You'll invariably end up having to bend pins manually.
Also, I'd rather that the RAM/ROM control pin be controlled electronically. Mechanical switches can bounce, and if the CPU happens to be executing RAM or ROM code at that point, you'll cause the machine to crash. With the transients it might produce, you just might crash it anyway.
I would also suggest "RAM write-through", as was done for the Commodore 64 and 128. That is, to copy ROM into RAM, you just do this:
(As a programmer for the 65816, I really had to think about how to write the above code. The 65816 would handle this problem with the greatest of ease!) Anyway, after the loop completes, you're then free to soft-switch out the ROM, and then you can "patch" the ROM via its RAM copy.
Also, I'd rather that the RAM/ROM control pin be controlled electronically. Mechanical switches can bounce, and if the CPU happens to be executing RAM or ROM code at that point, you'll cause the machine to crash. With the transients it might produce, you just might crash it anyway.
I would also suggest "RAM write-through", as was done for the Commodore 64 and 128. That is, to copy ROM into RAM, you just do this:
Code: Select all
LDY #$80 ; adjust as needed
STY $01
LDY #$00
STY $00
copyLoop:
LDA ($00),Y ; read from ROM
STA ($00),Y ; write to RAM
INY
BNE copyLoop
INC $01
BNE copyLoop
I will test fit a header on my boards from ExpressPCB when I get home. if it doesn't fit well, then the 90 degree pins might be best.
As far a switching the RAM/ROM, electronic bank switching would be nice, but I was going for simple. my thought was to have some code running in the lower RAM that waits in a loop and prompts the user to toggle the switch now, and press enter when done.
The idea here being to copy ROM to RAM, or download your OS from the host into upper RAM, then switch control once. the ROM could have the code needed and perform the copy down to RAM.
If you have a low-complexity bank switch method, I'm all for using it.
As stated, any write to the upper 32k would be to RAM1, regardless of the switch position. (RAM write through). We could modify that as well... remove the A7 input and replace it with another switch.
We can certainly tweek this. We may even want to look into a GAL 22V10
to carry the bank select logic as well as the address decoding.
Daryl
As far a switching the RAM/ROM, electronic bank switching would be nice, but I was going for simple. my thought was to have some code running in the lower RAM that waits in a loop and prompts the user to toggle the switch now, and press enter when done.
The idea here being to copy ROM to RAM, or download your OS from the host into upper RAM, then switch control once. the ROM could have the code needed and perform the copy down to RAM.
If you have a low-complexity bank switch method, I'm all for using it.
As stated, any write to the upper 32k would be to RAM1, regardless of the switch position. (RAM write through). We could modify that as well... remove the A7 input and replace it with another switch.
We can certainly tweek this. We may even want to look into a GAL 22V10
to carry the bank select logic as well as the address decoding.
Daryl
kc5tja wrote:
If you intend on running one, and only, one application over the link, that's fine. Otherwise, you're MUCH better off going with TCP/IP. This way, you at least could manage multiple logical connections to the computer (e.g., using a terminal of some kind at the same time as transferring a file). Implementations of TCP/IP are freely available as part of the Contiki operating system, for example, or self-standing via the uIP package.
I wasn't thinking of making my little box multitask, it seems like overkill for something with less than 64KB of user memory (I may have 2 tiered device drivers, but that's it). The "beauty", if you can call it that, of my idea is that it lets you multiplex a moderately complex UI and binary data transfer over a single cable, and I can access all that from a PC/Mac using a standard-ish app (a terminal emulator) without the overhead of something like an X server. I'm going to assume there's a chip or demo board somewhere that works the same as the USB245, but for ethernet instead of USB. If I used that instead of USB or RS232, how would I access my little box from a PC?
faybs wrote:
Now I've seen everything 
Seriously...
It depends on your application. If you're only doing one thing at a time (not to be confused with running one program at a time), then a terminal interface is fine. Otherwise, you will need to multiplex multiple data streams over that single cable. For utter simplicity, I'm a fan of ATM, but you'll need to write a custom ATM switch on the PC. Probably not what you're looking for.
IF, and I repeat this, *IF* you do go with TCP/IP over the serial interface, you can use PPP or (preferably, since it's simpler) SLIP, both of which I know Windows supports via its dial-up networking support. You may need to install it separately on modern versions of Windows, since few people have modems anymore.
For Linux, it's the same thing -- you need to set up a PPP or SLIP driver.
Quote:
I wasn't thinking of making my little box multitask, it seems like overkill for something with less than 64KB of user memory (I may have 2 tiered device drivers, but that's it).
Note that you're not going to get Unix Workstation Class Networking
Quote:
The "beauty", if you can call it that, of my idea is that it lets you multiplex a moderately complex UI and binary data transfer over a single cable, and I can access all that from a PC/Mac using a standard-ish app (a terminal emulator) without the overhead of something like an X server.
But there is nothing preventing a text-mode UI from being used with TCP/IP. In fact, I encourage you to "telnet uncensored.citadel.org" if you don't believe me.
Quote:
If I used that instead of USB or RS232, how would I access my little box from a PC?
That being said, let's suppose you find one that you can get working at all, let alone well. The simplest method of accessing the device is through telnet. A telnet connection is just a dumb socket connection -- no encryption at all, and unless the *server* on the other side asks for it, no need to password authenticate either. Yeah, there are options you can support to communicate things like terminal size, echo settings, etc. But those are extra credit items. Telnet is, at its core, an otherwise unadorned TCP stream that delivers raw bytes (usually with VT100 escape codes if it's text) from the device, and whatever you type in goes the other way. In other words, Telnet emulates a modem.
(Note that HTTP, SMTP (e-mail), POP3 and IMAP (also email), FTP, etc. all are just glorified telnet sessions. In fact, you can do this:-
Code: Select all
telnet www.google.com 80
Code: Select all
GET / HTTP/1.0
Code: Select all
telnet mail.yourdomain.com 110
USER <your username>
PASS <your password>
STAT ((tells you how many messages are waiting))
RETR n ((fetches message #n))
DELE n ((deletes message #n))
QUIT
- BitWise
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- Location: Berkshire, UK
- Contact:
8BIT wrote:
If you have a low-complexity bank switch method, I'm all for using it.
Daryl
Daryl
6502.org wrote:
Image no longer available: http://www.obelisk.demon.co.uk/forum/plds.gif
The second PLD subdivides the I/O page for the two VIAs (VIA & VIB), generates RD/WR signals and a flip-flop controlled ROM enable signal (ENB) which is initialised with a reset and cleared by a write to zero page.
Full schematics here:
http://www.obelisk.me.uk/forum/sch1.gif
http://www.obelisk.me.uk/forum/sch2.gif
Edit: Fixed URLs
Last edited by BitWise on Sat Feb 29, 2020 7:41 pm, edited 1 time in total.
Andrew Jacobs
6502 & PIC Stuff - http://www.obelisk.me.uk/
Cross-Platform 6502/65C02/65816 Macro Assembler - http://www.obelisk.me.uk/dev65/
Open Source Projects - https://github.com/andrew-jacobs
6502 & PIC Stuff - http://www.obelisk.me.uk/
Cross-Platform 6502/65C02/65816 Macro Assembler - http://www.obelisk.me.uk/dev65/
Open Source Projects - https://github.com/andrew-jacobs
@kc5tja
Hmm, that's quite interesting. I knew about telnet (used to play MUDs back in the day), but I always thought it was straight text with no control characters other than what low ascii gives you. When I say UI, I mean something like the old Borland text mode stuff, implemented using something like the C64's "[home][crsrdn][crsrdn][crsrright]hello", or maybe something a bit more complex; but definitely not pixels. If telnet does give you that sort of control I may go for that, but I'll have to decide if the added complexity is worth it for my very limited first effort.
What do I mean by a two tiered device driver? it's a fairly common technique, but it's got a zillion names so you probably know it by a different one. Basically, you write the device driver to have two parts, the bit banging part which usually consists of little more than an interrupt handler and must finish quickly so as not not affect the machine's performance; and the calculating part which is run on a lower priority interrupt or as a regularly scheduled task. This part does all the more time consuming stuff, since it's not as timing critical. For example, consider a synchronous serial comms port using two VIAs. You'd have a SR interrupt that gets triggered when a byte gets shifted in, the ISR would fetch the byte from the VIA's SR and append it to a queue so as to free up the VIA as soon as possible so it can receive the next byte. There would also be another interrupt on Timer 1, set up to trigger at say 50Hz. The ISR for this other interrupt would get the bytes from the queue, run a CRC calculation to make sure the data arrived correctly and set some flags based on the message. You could have done all this in the SR ISR, but that ISR would either have been a lot more complex to handle the case where a new byte arrives while it's still busy calculating, or you would have had to slow down communications to make sure no bytes are lost or maybe implement a handshaking protocol. Instead, since the SR ISR is so small that it can do its job while the next byte is still getting shifted in, we can have a fast and simple device driver.
About Forth... I'll have to look into it. I'm not a huge fan of reverse Polish notation (especially after I found out how simple it is to convert regular "human" infix notation into postfix), but it looks like 65xx CPUs seem to be optimized for the Forth way of doing things. Definitely worth looking into.
Hmm, that's quite interesting. I knew about telnet (used to play MUDs back in the day), but I always thought it was straight text with no control characters other than what low ascii gives you. When I say UI, I mean something like the old Borland text mode stuff, implemented using something like the C64's "[home][crsrdn][crsrdn][crsrright]hello", or maybe something a bit more complex; but definitely not pixels. If telnet does give you that sort of control I may go for that, but I'll have to decide if the added complexity is worth it for my very limited first effort.
What do I mean by a two tiered device driver? it's a fairly common technique, but it's got a zillion names so you probably know it by a different one. Basically, you write the device driver to have two parts, the bit banging part which usually consists of little more than an interrupt handler and must finish quickly so as not not affect the machine's performance; and the calculating part which is run on a lower priority interrupt or as a regularly scheduled task. This part does all the more time consuming stuff, since it's not as timing critical. For example, consider a synchronous serial comms port using two VIAs. You'd have a SR interrupt that gets triggered when a byte gets shifted in, the ISR would fetch the byte from the VIA's SR and append it to a queue so as to free up the VIA as soon as possible so it can receive the next byte. There would also be another interrupt on Timer 1, set up to trigger at say 50Hz. The ISR for this other interrupt would get the bytes from the queue, run a CRC calculation to make sure the data arrived correctly and set some flags based on the message. You could have done all this in the SR ISR, but that ISR would either have been a lot more complex to handle the case where a new byte arrives while it's still busy calculating, or you would have had to slow down communications to make sure no bytes are lost or maybe implement a handshaking protocol. Instead, since the SR ISR is so small that it can do its job while the next byte is still getting shifted in, we can have a fast and simple device driver.
About Forth... I'll have to look into it. I'm not a huge fan of reverse Polish notation (especially after I found out how simple it is to convert regular "human" infix notation into postfix), but it looks like 65xx CPUs seem to be optimized for the Forth way of doing things. Definitely worth looking into.
BitWise wrote:
The second PLD subdivides the I/O page for the two VIAs (VIA & VIB), generates RD/WR signals and a flip-flop controlled ROM enable signal (ENB) which is initialised with a reset and cleared by a write to zero page.
I strongly prefer just using a bit from a VIA somewhere. You just can't get any cheaper than that. If that takes away from bits you'd use for other things, then use the VIA's serial port to talk to one or more 74595s, with a single bit to publish the serial data when you're done loading it.
The simplest possible design always fulfills two goals: it communicates intent to the code or schematic reader and it involves the least number of design tradeoffs.
- BitWise
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kc5tja wrote:
BitWise wrote:
The second PLD subdivides the I/O page for the two VIAs (VIA & VIB), generates RD/WR signals and a flip-flop controlled ROM enable signal (ENB) which is initialised with a reset and cleared by a write to zero page.
I strongly prefer just using a bit from a VIA somewhere. You just can't get any cheaper than that. If that takes away from bits you'd use for other things, then use the VIA's serial port to talk to one or more 74595s, with a single bit to publish the serial data when you're done loading it.
The simplest possible design always fulfills two goals: it communicates intent to the code or schematic reader and it involves the least number of design tradeoffs.
In an earlier post I suggested we could use another processor to take control of the bus and load the O/S into the RAM but this requires more glue logic to gate the control signals which aren't affected the the bus enable signal (and the data/address bus lines on the older rockwell chips). I like the idea and am using it in another design but I had to switch to much bigger PLCC based PLDs to get the number of I/O lines I need.
As for using logic controlled thru one the VIAs, yes you could but you'd also need logic around it to make sure that the ROM is enabled on reset so I not convinced it ends up being any simpler than my two PLD design.
Andrew Jacobs
6502 & PIC Stuff - http://www.obelisk.me.uk/
Cross-Platform 6502/65C02/65816 Macro Assembler - http://www.obelisk.me.uk/dev65/
Open Source Projects - https://github.com/andrew-jacobs
6502 & PIC Stuff - http://www.obelisk.me.uk/
Cross-Platform 6502/65C02/65816 Macro Assembler - http://www.obelisk.me.uk/dev65/
Open Source Projects - https://github.com/andrew-jacobs
BitWise wrote:
The first PLD does coarse address decoding for two 32K memory areas (LWR & UPR), zero page (ZP), an I/O page (I/O) and a switchable 4K ROM (ROM).
The second PLD subdivides the I/O page for the two VIAs (VIA & VIB), generates RD/WR signals and a flip-flop controlled ROM enable signal (ENB) which is initialised with a reset and cleared by a write to zero page.
The second PLD subdivides the I/O page for the two VIAs (VIA & VIB), generates RD/WR signals and a flip-flop controlled ROM enable signal (ENB) which is initialised with a reset and cleared by a write to zero page.
Daryl