Advice needed on SBC

[Floopy]

GaBuZoMeu wrote:

Hi Floopy,

I don't want to sound sarcastic but me thinks your computer is very hard to use: you have no input nor output provided So far it is just capable of drawing current (OK, there is something, but I believe that is not your intention )

Next your reset circuitry won't work (IMHO). As I see it, C6 pulls /RESET high briefly after power on and is then charged through R2 causing /RESET to see 0V. IOW you need to switch R2 and C6 to have a brief "0" at /RESET and then a "1" during runtime. I would suggest that you add a diode (1N4148 o.e.) parallel to R2 (cathode at +5V). The diode would allow C6 to discharge quickly into Vcc when you turn Vcc off. Otherwise all charge went through /RESET and internal protection diodes into Vcc.

If you use a 74HC139 (instead of your 138) your map would consist of four 16K blocks. Using 8K RAM/EEPROM they would simply appear twice in their 16K block. Using 32K devices you could use just one half (you need to strap the A14 pin of that devices to either GND or Vcc). You had then two 16K regions still available, one for onboard I/O, one for your expansion port. The other half of the 139 can be used to generate a qualified /WR (qualified by PHI2) for your RAM.


Good Luck!

Me forgot to mention it's for heating office!

>Next your reset circuitry won't work
I was just trying to save components. It looked so simple I thought I would do it that way and it worked in the "test" run. I just had a 6502 with a NOP hard wired and it seemed to work. I've seen a 555 being used also.

>If you use a 74HC139 (instead of your 138)
>

BigDumbDinosaur wrote:

Floopy wrote:

The memory is sectioned into 8 banks each 8192Bytes. I'm using a De-MUX (74138) to do the selecting. It's using the upper 3 bits of addressing.

Why? What is wrong with using linear addressing in a single (larger) SRAM? That 74HC138 won't be doing you any favors with its slow performance. Using a single 32k × 8 SRAM, you can reduce your parts count and you'll gain timing headroom should you later decide to run a faster clock. Take a look at Alliance's AS7C256B-15PIN 32k × 8 SRAM, which is in a DIP28 package and has a 15ns access time.

The idea was that I would have enough memory to slot any experimental device. If I have just two 32K banks then I can't do too much. Also the datasheet for the 138 I'm using says a 13ns switching time.
http://www.ti.com/lit/ds/symlink/sn74ahct138.pdf
I do have some 139 and Alliance's AS7C256B-15PIN 32k × 8 SRAM. I had picked two options when it came to building. Either make 8Banks or have 2 with one being broken into two 16K.
For now I just want to run this a 1Mhz. Speed performance is not currently in mind. It's just an experimental SBC, meaning it's for learning how to use the 65C02 to control other devices such as a 65C22 or an LCD 16*4.

floobydust wrote:

On yet another note, you should look more closely at the expansion connector... you're not bringing any of the signals used for Reset, IRQ or NMI. So if you plan on using some typical I/O devices, you'll likely need these to get them working properly. I would also suggest using something like a DS-1815 Reset chip instead of the RC setup and add a momentary switch as well so you can easily reset the CPU and any other I/O devices.

I will look into it. The reset circuitry needs some work done

BigDumbDinosaur wrote:

Taking the MPU's buses and signals off-board is not recommended. Garth explains why right here.

The original idea was to run it on a pin header to hook it to another board. I think I will do what they do on floppy drives. Alternate between ground and a signal.

I should have mentioned that programming is not my strong point either.

-Thank you!

[GARTHWILSON]

Floopy wrote:

The idea was that I would have enough memory to slot any experimental device. If I have just two 32K banks then I can't do too much.

Would these experimental devices have actual memory in them? Can whatever is loaded in that memory reside in your main memory on the main board instead (for example, drivers for the I/O)? If the experimental stuff would go through I/O ICs anyway, note that the initial simple diagram BigEd posted will serve for up to ten 65xx I/O ICs, with no additional logic. The 6502 primer tells how.

[BigDumbDinosaur]

Floopy wrote:

BigDumbDinosaur wrote:

Floopy wrote:

The memory is sectioned into 8 banks each 8192Bytes. I'm using a De-MUX (74138) to do the selecting. It's using the upper 3 bits of addressing.

Why? What is wrong with using linear addressing in a single (larger) SRAM? That 74HC138 won't be doing you any favors with its slow performance. Using a single 32k × 8 SRAM, you can reduce your parts count and you'll gain timing headroom should you later decide to run a faster clock. Take a look at Alliance's AS7C256B-15PIN 32k × 8 SRAM, which is in a DIP28 package and has a 15ns access time.

The idea was that I would have enough memory to slot any experimental device.

"Experimental device" sounds too vague to be tying up large segments of the MPU's address space the way you are doing. Better to set up some I/O ports (which is a good place to use the 74*138 decoder) and not directly expose the MPU's buses to your experiments. The 65C22 can be used for this purpose, a topic that Garth extensively covers on his website.

It sounds as though you are designing in excessive complexity. The likelihood of a first-time unit not working is roughly proportional to the square of the degree of convolution. All kidding aside, learn to fly a Piper Cub before you climb into the cockpit of a 747. Your mistakes will be easier to diagnose and correct.

Quote:

If I have just two 32K banks then I can't do too much.

Au contraire! What you are trying to do is lay out a memory map that doesn't fit the 65C02 very well. The "classic" memory map would have a modicum of contiguous RAM—which would encompass the all-important zero and stack pages, followed by some amount I/O, followed by ROM. This can be accomplished with minimum of glue logic.

With a little more glue logic, you can have a more expansive memory map. For example:

Code: Select all

$0000-$CFFF  RAM, 52KB contiguous
$D000-$DFFF  I/O,  4KB
$E000-$FFFF  ROM,  8KB

That's the memory map I used in my POC V1 design, accomplished with no more than two gate delays from the address bus to the chip selects for RAM and ROM, and a maximum of three gate delays between the address bus and I/O hardware. In V1, I used a 128KB SRAM, and simply ignored the part of it I wasn't interested in using. That was also the case for ROM—I use a 32KB EPROM, but only decoded 8KB of it.

Within the I/O block, I arranged the following:

Code: Select all

$D000	Dual UART
$D100	Real-time clock
$D200	SCSI PIO data port
$D300	SCSI DMA data port
$D400	SCSI DMA request
$D500	Spare I/O A
$D600	Spare I/O B
$D700	Spare I/O C

In the world of computers, I/O is everything. A computer that can compute but can't communicate is of very limited usefulness.

Quote:

Also the datasheet for the 138 I'm using says a 13ns switching time. http://www.ti.com/lit/ds/symlink/sn74ahct138.pdf

Your schematic appears to be identifying that part as a 74HC138. That device has much different timing specs than the 74AHCT138—also, the 'AHCT138 has TTL-compatible inputs, which is not the case for the 74HC138. Those letters in between the '74' and the '138' do matter, y'know.

Incidentally, it's best if you post your schematics in monochrome. We have one or two members who have color-blindness.

Quote:

floobydust wrote:

I would also suggest using something like a DS-1815 Reset chip instead of the RC setup and add a momentary switch as well so you can easily reset the CPU and any other I/O devices.

I will look into it. The reset circuitry needs some work done

floobydust meant the Maxim DS-1813, which is a handy little gadget in a TO-92 package. I also use it as a push button debouncer for the NMI circuit in my POC units.

reset_controller_ds1813.pdf

Maxim DS-1813 Reset Controller

(206.15 KiB) Downloaded 236 times

Quote:

BigDumbDinosaur wrote:

Taking the MPU's buses and signals off-board is not recommended.

The original idea was to run it on a pin header to hook it to another board. I think I will do what they do on floppy drives. Alternate between ground and a signal.

Remember my above comment about the Piper Cub and the 747? I do not recommend you do this. Parasitic capacitance will quickly degrade signal quality and may result in a DOA unit. Also, if the cable has any significant length to it, you will be grappling with problems caused by transmission line effects, which only experts can usually resolve. I think you will quickly end up in over your head.

Quote:

I should have mentioned that programming is not my strong point either.

Well, programming is something you will have to bone up on if you are going to write enough firmware for your machine to make it do something. Fortunately, many of use are fluent in the 6502 assembly language and can help you.

[Floopy]

GARTHWILSON wrote:

Floopy wrote:

The idea was that I would have enough memory to slot any experimental device. If I have just two 32K banks then I can't do too much.

Would these experimental devices have actual memory in them? Can whatever is loaded in that memory reside in your main memory on the main board instead (for example, drivers for the I/O)? If the experimental stuff would go through I/O ICs anyway, note that the initial simple diagram BigEd posted will serve for up to ten 65xx I/O ICs, with no additional logic. The 6502 primer tells how.

You are probably right. I was thinking of having slots where whatever device I would need would be slotted, but if I have I/O then I can control just about whatever I need to control. (that was repetitive) This is the reason why I wanted to ask first, the design is something I made up on a boring day and decided a schematic was note worthy. This is my first time doing something like this.

I'll use a 139 to select between RAM/ROM and use the schematic given by Biged to interface the I/O.

Is the 6530 an interesting device to mess around with?

-Thanks

[Floopy]

Didn't notice you posted after I submitted.

I realize my mistake now. As I said the obvious is prone to happen, I'll do some more digging and see what I can come up with. The design I had can be scrapped, not much to salvage.

Also I did keep in mind timing, that's why I had bought the right parts.

> The 65C22 can be used for this purpose, a topic that Garth extensively covers on his website.
What happens when you don't read documents thoroughly. I just used the parts I needed and filled the rest with what I knew.

I will work on it. Don't know what I would have done without you all.

[Chromatix]

A tip that came up in an earlier thread is to use a 74x85 "4-bit Magnitude Comparator" to decode a simple RAM-I/O-ROM split address space.

Just attach one input to the high-order address lines, tie the other input to the high-order address of your I/O window, and it will produce three select lines - one for the I/O window itself (equality), one for the ROM (greater) and one for the RAM (less). If you use all four bits, your I/O window will end up being 4KB wide, and you can subdivide it further using '138s.

Also don't worry too much if your chosen RAM or ROM chip doesn't completely fill the spaces selected for them. Just wire up the address lines you have, and understand that the memory will "mirror" at different addresses. Writing or reading any of the mirrors will reflect the contents of all of them.

[Floopy]

Chromatix wrote:

A tip that came up in an earlier thread is to use a 74x85 "4-bit Magnitude Comparator" to decode a simple RAM-I/O-ROM split address space.

Just attach one input to the high-order address lines, tie the other input to the high-order address of your I/O window, and it will produce three select lines - one for the I/O window itself (equality), one for the ROM (greater) and one for the RAM (less). If you use all four bits, your I/O window will end up being 4KB wide, and you can subdivide it further using '138s.

Also don't worry too much if your chosen RAM or ROM chip doesn't completely fill the spaces selected for them. Just wire up the address lines you have, and understand that the memory will "mirror" at different addresses. Writing or reading any of the mirrors will reflect the contents of all of them.

My only issue is that where I live I need to buy everything online. I also don't have an arsenal of spare parts that are lying around in drawers. I usually get what I need from mouser, but I like to combine projects that way I pay a low shipping charge. I will keep that in mind. I already have all the parts that I need to get started.

[BillO]

Hi Floopy - another cook to spoil your broth -

Floopy wrote:

The reset circuitry needs some work done

If you have a 2N7000 MOSFET you can create a workable reset. Schematic attached.

Floopy wrote:

The original idea was to run it on a pin header to hook it to another board. I think I will do what they do on floppy drives. Alternate between ground and a signal.

Your only looking to go at 1MHz, so I think you can get away with a little bus if you want. Keep it sane and separate the signals on the bus from the CPU using buffers. Just plan to buffer it on the main board and keep the interconnecting cable short. You'll need to generate a Data Direction signal for the data bus buffers which will need to be bi-directional. It would be helpful to also bring Phi-2 to your bus as well as the signals you mentioned.

[Floopy]

There is probably an obvious answer to this...

Does anyone know of a good source on the 6522 VIA. I'm still not entirely sure how it works and how to interface it.

-Thanks

[BigDumbDinosaur]

Floopy wrote:

There is probably an obvious answer to this...

Does anyone know of a good source on the 6522 VIA. I'm still not entirely sure how it works and how to interface it.

-Thanks

Mouser sells the WDC 65C22.

[GARTHWILSON]

Floopy wrote:

Does anyone know of a good source on the 6522 VIA. I'm still not entirely sure how it works and how to interface it.

Besides where to buy some VIAs, it sounds like you're also looking for information. Many of the tips in my Tip of the Day column are about using the VIA. There's more on my site in various features and articles, especially in the Circuit Potpourri section of the 6502 primer

[Floopy]

GARTHWILSON wrote:

Floopy wrote:

Does anyone know of a good source on the 6522 VIA. I'm still not entirely sure how it works and how to interface it.

Besides where to buy some VIAs, it sounds like you're also looking for information. Many of the tips in my Tip of the Day column are about using the VIA. There's more on my site in various features and articles, especially in the Circuit Potpourri section of the 6502 primer

Thank you Garth, my lack of English skills is showing. I should have worded the sentence better. I will do some digging, there seems to be more info on the forum than I thought there was. I usually get what I need from Mouser anyway, it's nice when you open a package and it's all inside anti-static bags.

[Floopy]

I went and did a little more research. I finally have a (partial) schematic. I still need to work on the layout, the I/O is far from complete and I need to put some headers to select what type of memory I'm using. It's starting to look more and more like the schematic Garth has on his primer. Maybe because I got most of the information there. As long as he's alright with it.

I'm just asking for some critique.
Keep in mind:
-I didn't want to use a 74132 for the reset and banking. Reason being is that I already have a lot of 7414 and 7400 lying in my parts drawer.
-I know it's not complete.

Question to consider:
-Would it be useful to have headers for the Address lines and Data bus? I just want to experiment with other devices. I have a few 6551 lying around. I know that I hinted at the idea, but it would just be for something like bread boarding.
-I put two LED on the board: one for power, the other for the reset line. Is there anywhere else where I should add some?

Anyway, let me know!
Edit: One other reason why I want to put headers for the Address lines and Data bus is because I can hook up my logic analyzer with a 6502 disassembler. Great for trouble shooting.

[BigDumbDinosaur]

Floopy wrote:

I went and did a little more research. I finally have a (partial) schematic...

Can you please post your schematic in monochrome?

[Floopy]

BigDumbDinosaur wrote:

Floopy wrote:

I went and did a little more research. I finally have a (partial) schematic...

Can you please post your schematic in monochrome?

Sure? I updated a few things.

I'm not sure what to do with IRQ(not) on the 6522?

IRQ needs to be hooked up to pin 13 on the 6502.
Quoting form datasheet:"To access a selected W65C22 register, CS1 must be logic 1 and CS2B must be logic 0".
That's why CS1 is tied to A13