I was wondering if anyone here would be able to help me get my feet wet in understanding the die shot for the 6561 VIC video chip as downloadable from the visual6502.org web site:

http://visual6502.org/images/pages/MOS_6561_VIC_die_shots.html

I've been staring at it for a couple of weeks now and reading up on various related topics, such as NMOS, integrated circuits and the materials used in their construction, and I've been playing around a bit with the Electric VLSI tool.

I'm aware of the partially labelled version of the die shot available here:

http://segher.ircgeeks.net/vic/

That version makes it a lot easier to start to see what is going on. But beyond being able to work out the address lines, data lines, Vdd and gnd, it is all a bit of a mystery. The diagram labels the memory mapped registers, so it is fairly easy to spot where those are, but trying to spot individual transistors is something I'm not yet familiar with. Segher, who created the labelled version of the die shot, had been able to reverse the logic of the Y decode section back in 2011, as mentioned here:

http://www.softwolves.com/arkiv/cbm-hackers/15/15524.html

I've sent Segher an email but haven't yet received a reply back. So in the mean time I was wondering if anyone else could provide some tips.

Some initial questions: Do the pink and green colours actually have some meaning? For a while I was wondering if the pink was polysilicon and the green was the doped diffusion areas, but now I'm wondering if that is wishful thinking since I read somewhere that colours can show up due to thin film interference. But even if this is the case then the colour might hopefully relate to the depth and therefore to the type of material, but even this might be wishful thinking. Could the colours relate to something else then? Could it be that the pink and green are just additional metal layers? Did NMOS chips of that time have multiple metal layers?

The white areas are obviously the top metal layer. I'm assuming that the dark grey areas are due to the insulation layer immediately below the metal layer. The brown areas are usually where the pink areas are showing through only the oxide rather than through both the oxide and metal.

One thing that I have just noticed that is probably important is that the contacts down to the green layer are usually from the power lines.

Lance

Could you post a suitably small crop? I can talk you through what's there.
Cheers
Ed

Let's give this a go. It is probably one of the more cluttered parts of the die shot, but I think in this case we know what should be here. It is apparently register CR2, so I'm guessing that there is an 8-bit flip flop in there somewhere. Those 8 short vertical metal lines look suspiciously related. The bits showing up underneath those must therefore be components of the flip flops? There is definitely a pattern there that is repeated 8 times.

The bit near the top of the image seems to be selecting the register based on the address line values but where all the transistors are I have no idea.

It is possible that the labels are obscuring some of the detail, so I could post the same section from the unlabelled version if you think it would be required. I saved the image as jpeg so as to make it a lot smaller, but it has lost the crispness of the labels. The f1 label towards the bottom I think must be one of the clock lines, and the wide white metal bit at the bottom is gnd (if I have followed the line correctly). Also the thicker white line through the middle is gnd. Most of the narrower lines horizontally across the middle are either address lines or data lines. I think I haven't quite captured enough of those lines. The horizontal metal lines (as shown in the attachment) go in this order from the top: D2, D3, A0in, #A0in, A1in, #A1in, A2in, GND, #A2in, A3in, #A3in, ?, ?, D4, D5, ?, D6, D7 (where the ? are where I'm not sure yet). D1 and D0 appear in the original image immediately above this cropped section.

As I say, the original image is clearer than this, but the image, even for this small section, was going to be quite large as a PNG.

OK, let's look at a small portion:


You're quite right that colours come from thin-film effects: in some processes poly is red and active is green, in some processes it's the other way around.

If we start by recognising the typical shapes of poly and active (diffusion) where they are not covered by metal, it will be easier to later identify them where they are covered.

Poly is generally thin, whereas active is usually larger: poly is going from one place to another whereas active is covering an area. The crucial thing is that poly crosses active to make a transistor: so it overlaps an active region a bit and then stops. Both poly and active will surround any contacts - so spotting the contacts first will help. If there's ambiguity about where the edge of active is, looking at the poly will often help.

In this case poly is red whereas active is blueish. The field oxide (the negation of active) is greenish. There's just one layer of metal, and therefore only one type of contact cut which connects metal down to whatever is below. This process also allows for a butted or buried contact, where poly connects to active (without making a transistor)

I've traced the edges of some active here, and the centrelines of some poly - there's are two mirrored versions of the same structure which should help you see which edges I've followed:


As every contact cut must connect from metal down to something, you can use that to orientate yourself as to whether you're inside a shape or outside it.

The L-shaped fat poly towards the right is indicating a weak transistor: normally that will prove to be a pullup. It's still poly crossing active, but it looks like a thin meander of active running under a big rectangle of poly.

The fat poly to the left (inverted L shape) is certainly a pull up. In this case at the north edge where the active approaches the poly you see a faintly outlined rectangle. That's the buried contact: the poly and active are electrically connected. That's typical for the output of a gate: the poly continues south as a normal width line, carrying that output signal.

Once you're under metal, you need to look at edges and see which shape and layer they must logically belong to.

Hope that helps a bit: I feel I could have done better...

Cheers
Ed

Thanks Ed. That is very helpful. It might take me a few days to look over this in detail. I may well have some additional questions.

What I might try to do is recreate the physical layout for this 8 bit register inside the Electric VLSI tool. That seems like as good a way as any of keeping track of what I've deduced so far.

Cheers,
Lance

Yes, if you remake the layout, extract the circuit and simulate it, that would be very good!
If Electric doesn't do it all for you, Peter Monta has made some tools to help with this kind of thing: https://github.com/pmonta/FPGA-netlist-tools
I believe I used his tools to perform this SPICE simulation of the 6502: viewtopic.php?p=13550#p13550
I recommend you check out John McMaster's blog too: http://uvicrec.blogspot.co.uk/
Let us know how you get on!
Cheers
Ed

This post might be of interest too.

I hope people don't mind me resurrecting a topic I posted over 5 years ago. Only my 4th post, but I wanted to bring people's attention to a series of posts I've made over at the VIC 20 Denial Forums regarding reversing the logic of the 6561 VIC die shot:

http://sleepingelephant.com/ipw-web/bul ... =11&t=8733

and:

http://sleepingelephant.com/ipw-web/bul ... =45#p86169

My understanding has progressed a lot since I began doing this back in 2016, to the point where I've reversed most of the chip. I wanted to thank @BigEd for his help in 2013 when I was still feeling my way with this. Your tips were very helpful. Sorry that it has been so long to report back on my progress.

Thanks for the pointers, Lance, and thanks for the flowers! Glad to hear you stuck at it. I'll read those threads... probably tomorrow.

BTW, on the question of whether diffusion continues beneath poly, as discussed here:
http://sleepingelephant.com/ipw-web/bul ... 073#p98375

I'd say there are two perspectives. From the perspective of the final chip, as seen in the cross-section, the diffusion doesn't continue under the gate, and so the source and the drain areas are not connected. Indeed, that's the intent: the gate then controls the formation of a temporary channel between them.

But, from the design, mask-making and fabrication perspective, the diffusion is drawn as being continuous from source through gate to drain. The reason - I think I have this right - is that gates these days are self-aligned. In very early MOS processes, the gate had to be aligned over the gap between the source and drain. This made processes more difficult, more sensitive, less scalable. The modern process constructs the source-channel-drain area first, by where the field oxide is grown, then the polysilicon, and the presence of polysilicon acts as a mask to determine where the gate oxide is and where the diffusion goes.

I probably haven't explained it too well. But the point is that the design - the polygons - do indeed go over the whole transistor, and the masks are made from the polygons, then the chip is made with the mask.

It sounds like I have been drawing around the polysilicon and diffusion in the right way then. I started out like that mainly due to how the Mead/Conway book presented things. Good to know then that this appears to be how things are normally done. I do wonder though whether the polygons I have been drawing over the past couple of years will end up being useful, or whether perhaps I should have been drawing them a bit differently. I didn't spend much time at looking how other people were doing it before I got stuck in. Is there a standard approach to drawing the polygons that people follow when reversing a chip like this?

As it happens, I think I'd tackle the sketching a different way - not that I've ever done very much of this sort of annotation of die photos. I'd do it by painting, with a square brush about the width of the layer in question, and with the colour being translucent. I'd paint a lot of poly in one go, and a lot of diffusion, and so on, because context switching is time-consuming. Like you, and like anyone, I'd be looking at the edges and the patterns of the shapes to understand what is going on, but rather than capturing it vertex by vertex as an outline, I'd want to capture it by painting the interior.

Inkscape seems to be a good choice of tool: I think it can handle translucency and multiple layers.

We did have an idea and an attempt to crowd-source this part of recapturing layouts, but we didn't quite get there. The interface we had was to drag rectangles out, using opposite corners. The idea was to have the minimum number of actions to capture a polygon. The rectangles would overlap, and be merged programmatically to make the polygons. (We also had a version where you clicked first one end, then the other end, of a track of the appropriate width.)

There's a very half-baked demo here:
http://biged.github.io/crowdsource-poly ... =1&itype=p
with my fork of the client repo here
https://github.com/BigEd/crowdsource-polygons
and the server repo here
https://github.com/BigEd/crowdsource-server

(Either way, once you have the shapes, whether they be hollow or filled, they could be analysed and re-presented as a visual simulation like visual6502, or built up as a scaled-up demo like MOnSter6502.)